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________________________________________________________ maxim integrated products 1 some revisions of this device may incorporate devi ations from published specifications known as errata. multiple revisions of any device may be simultane ously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-464 2, or visit maxim?s website at www.maxim-ic.com. DS3104-se line card timing ic with synchronous ethernet support general description the DS3104-se is a low-cost, feature-rich timing ic for line cards with synchronous gigabit ethernet (gbe), 10-gigabit ethernet (10gbe), and fast ethernet ports. itu-t recommendation g.8261 (formerly g.pactiming) specifies that network synchronization can be carried over packet links by synchronizing the bit clock of the physical layer as is currently done on sonet/sdh links. the DS3104-se enables synchronization in ethernet line cards in both the transmit and receive directions. in the transmit direction, the device accepts traditional sonet/sdh system clocks such as 19.44mhz from redundant system timing cards and synthesizes frequency-locked xmii clock rates, such as the 125mhz gtx_clk for gbe gmiis. each ethernet phy then synthesizes a transmit bit clock that is frequency-locked to the xmii clock, and thus to the system clock and network clock. in the receive direction, each phy divides down the recovered bit clock to produce the receive xmii clock. the DS3104-se accepts the xmii clock from any of several ethernet ports and forwards a frequency-locked system clock, such as 19.44mhz, to the system timing cards. sonet/sdh ports are also supported. applications line cards with any mix of synchronous ethernet and sonet/sdh ports in wan equipment including mspps, ethernet switches, routers, dslams, and wireless base stations ordering information part temp range pin-package DS3104gn -40 c to +85 c 81 csbga (10mm) 2 DS3104gn+ -40 c to +85 c 81 csbga (10mm) 2 + denotes a lead-free/rohs-compliant package. features ? timing card to line card path ? two input clocks from master and slave timing cards (lvds/lvpecl or cmos/ttl) ? optional frame sync inputs and outputs ? continuous input clock quality monitoring ? hitless reference switching, automatic or manual ? holdover on loss of all inputs ? programmable pll bandwidth, 0.1hz to 400hz ? frequency conversion between sonet/sdh rates and ethernet mii/gmii/xgmii rates ? up to 7 output clocks: 3 cmos/ttl ( 125mhz), 2 lvds/lvpecl ( 312.50mhz), and 2 dual cmos/ttl and lvds/lvpecl ? line card to timing card path ? up to 8 input clocks: 4 cmos/ttl ( 125mhz) and 4 lvds/lvpecl/cmos/ttl ( 156.25mhz) ? hitless reference switching, automatic or manual ? frequency conversion between ethernet mii/gmii/xgmii and sonet/sdh rates ? two output clocks to master and slave timing cards (cmos/ttl or lvds/lvpecl) ? genera l ? suitable line card ic for stratum 3/3e/4, smc, sec ? numerous input clock frequencies supported ethernet xmii: 2.5, 25, 125, 156.25mhz sonet/sdh: 6.48, n x 19.44, n x 51.84mhz pdh: n x ds1, n x e1, n x ds2, ds3, e3 frame sync: 2khz, 4khz, 8khz custom: any multiple of 2khz up to 131.072mhz, any multiple of 8khz up to 155.52mhz ? numerous output clock frequencies supported ethernet xmii: 2.5, 25, 125, 156.25, 312.5mhz sonet/sdh: 6.48, n x 19.44, n x 51.84mhz pdh: n x ds1, n x e1, n x ds2, ds3, e3 other: 10, 10.24, 13, 30.72mhz frame sync: 2khz, 8khz custom clock rates: any multiple of 2khz up to 77.76mhz, any multiple of 8khz up to 311.04mhz ? internal compensation for master clock oscillator ? spi? processor interface ? 1.8v operation with 2.5v/3.3v i/o (5v tolerant) rev: 072407
________________________________________________________________________________________ ds 3104-se 2 table of contents 1. standards compliance .......................................................................................................... 6 2. application example ............................................................................................................ ... 7 3. block diagram .................................................................................................................. ......... 8 4. detailed description ........................................................................................................... ... 9 5. detailed features .............................................................................................................. ... 11 5.1 i nput c lock f eatures ............................................................................................................... 11 5.2 t iming c ard to l ine c ard dpll f eatures (t0 dpll).............................................................. 11 5.3 l ine c ard to t iming c ard dpll f eatures (t4 dpll).............................................................. 11 5.4 o utput apll f eatures ............................................................................................................. 12 5.5 o utput c lock f eatures ............................................................................................................ 12 5.6 g eneral f eatures ..................................................................................................................... 12 6. pin descriptions ............................................................................................................... ....... 13 7. functional description ....................................................................................................... 17 7.1 o verview ............................................................................................................................... ..... 17 7.2 d evice i dentification and p rotection ..................................................................................... 18 7.3 l ocal o scillator and m aster c lock c onfiguration ............................................................. 18 7.4 i nput c lock c onfiguration ...................................................................................................... 19 7.4.1 signal format c onfiguration .................................................................................................... ............ 19 7.4.2 frequency conf iguration........................................................................................................ .............. 20 7.5 i nput c lock m onitoring ............................................................................................................ 21 7.5.1 frequency m onitoring ........................................................................................................... ............... 21 7.5.2 activity mo nitori ng ............................................................................................................ .................... 21 7.5.3 selected reference ac tivity monitoring ......................................................................................... ...... 21 7.6 i nput c lock p riority , s election and s witching ..................................................................... 22 7.6.1 priority conf iguration......................................................................................................... ................... 22 7.6.2 automatic select ion algorithm .................................................................................................. ........... 22 7.6.3 forced selection ............................................................................................................... ................... 23 7.6.4 ultra-fast refere nce switching ................................................................................................. .......... 23 7.6.5 external referenc e switchi ng mode.............................................................................................. ...... 24 7.6.6 output clock phase continuity during referenc e switching .............................................................. 24 7.7 dpll a rchitecture and c onfiguration .................................................................................. 25 7.7.1 t0 dpll stat e machine .......................................................................................................... ............. 26 7.7.2 t4 dpll stat e machine .......................................................................................................... ............. 29 7.7.3 bandwidth ...................................................................................................................... ...................... 31 7.7.4 damping factor................................................................................................................. ................... 31 7.7.5 phase dete ctors................................................................................................................ ................... 31 7.7.6 loss of phase loc k detection ................................................................................................... .......... 32 7.7.7 phase buil d-out ................................................................................................................ ................... 33 7.7.8 input to output (manu al) phase ad justment...................................................................................... .. 33 7.7.9 phase recali bration ............................................................................................................ ................. 33 7.7.10 frequency and p hase measurement................................................................................................ ... 34 7.7.11 input jitter tolerance ......................................................................................................... .................. 35 7.7.12 jitter and wander transfer ..................................................................................................... ............. 35 7.7.13 output jitte r and w ander ....................................................................................................... .............. 36 7.8 o utput c lock c onfiguration ................................................................................................... 37 7.8.1 signal format c onfiguration .................................................................................................... ............ 37 7.8.2 frequency conf iguration........................................................................................................ .............. 37 7.9 f rame and m ultiframe a lignment ............................................................................................ 45 7.9.1 sampling ....................................................................................................................... ....................... 45
________________________________________________________________________________________ ds 3104-se 3 7.9.2 resampling ..................................................................................................................... ..................... 45 7.9.3 enable ......................................................................................................................... ......................... 45 7.9.4 qualific ation .................................................................................................................. ....................... 46 7.9.5 output cloc k alignment ......................................................................................................... .............. 46 7.9.6 frame sync monitor............................................................................................................. ................ 46 7.9.7 syncn pins ..................................................................................................................... .................... 46 7.9.8 other configurat ion options .................................................................................................... ............ 47 7.10 m icroprocessor i nterface .................................................................................................. 47 7.11 r eset l ogic ............................................................................................................................. 51 7.12 p ower -s upply c onsiderations ............................................................................................. 51 7.13 i nitialization ............................................................................................................................ 51 8. register descriptions ......................................................................................................... 52 8.1 s tatus b its ............................................................................................................................... .. 52 8.2 c onfiguration f ields ................................................................................................................ 52 8.3 m ultiregister f ields ................................................................................................................. 52 8.4 r egister d efinitions ................................................................................................................. 53 9. jtag test access port and boundary scan ............................................................. 116 9.1 jtag d escription .................................................................................................................... 116 9.2 jtag tap c ontroller s tate m achine d escription ............................................................. 117 9.3 jtag i nstruction r egister and i nstructions ...................................................................... 119 9.4 jtag t est r egisters .............................................................................................................. 120 10. electrical characteristics............................................................................................ 121 10.1 dc c haracteristics ............................................................................................................. 121 10.2 i nput c lock t iming ............................................................................................................... 125 10.3 o utput c lock t iming ............................................................................................................ 125 10.4 spi i nterface t iming ............................................................................................................ 126 10.5 jtag i nterface t iming ......................................................................................................... 128 10.6 r eset p in t iming ................................................................................................................... 129 11. pin assignments ................................................................................................................ .... 130 12. package information ......................................................................................................... 132 13. acronyms and abbreviations ......................................................................................... 133 14. trademark acknowledgements .................................................................................... 134 15. data sheet revision history............................................................................................ 135
________________________________________________________________________________________ ds 3104-se 4 list of figures figure 2-1. typical a pplication example ........................................................................................ ............................. 7 figure 3-1. DS3104-se f unctional diagram ....................................................................................... ........................ 8 figure 7-1. dpll block diagram ................................................................................................. .............................. 25 figure 7-2. t0 dpll st ate transition diagram ................................................................................... ...................... 27 figure 7-3. t4 dpll st ate transition diagram ................................................................................... ...................... 30 figure 7-4. fsync 8khz options................................................................................................. ............................. 44 figure 7-5. spi cloc k phase options ............................................................................................ ............................ 49 figure 7-6. spi bu s transactions............................................................................................... ............................... 50 figure 9-1. jtag block diagram................................................................................................. ............................ 116 figure 9-2. jtag tap co ntroller stat e machine .................................................................................. .................. 118 figure 10-1. recomm ended termination for lvds pins ............................................................................. ........... 123 figure 10-2. recommended te rmination for lvpecl signal s on lvds i nput pins .............................................. 123 figure 10-3. recomm ended termination for lvpecl- compatible ou tput pins .................................................... 124 figure 10-4. spi inte rface timi ng diagram ...................................................................................... ....................... 127 figure 10-5. jtag timing diagram............................................................................................... .......................... 128 figure 10-6. reset pi n timing diagram .......................................................................................... ........................ 129 figure 11-1. pin a ssignment diagram............................................................................................ ......................... 131
________________________________________________________________________________________ ds 3104-se 5 list of tables table 1-1. applicab le telecom standards........................................................................................ ........................... 6 table 6-1. input clo ck pin desc riptions ........................................................................................ ............................ 13 table 6-2. output cl ock pin descriptions....................................................................................... ........................... 14 table 6-3. global pin descri ptions ............................................................................................. ............................... 15 table 6-4. spi bus m ode pin desc riptions ....................................................................................... ........................ 15 table 6-5. jtag inte rface pin de scriptions ..................................................................................... ......................... 16 table 6-6. power-supp ly pin descriptions ....................................................................................... ......................... 16 table 7-1. input clock capab ilities ............................................................................................ ................................ 19 table 7-2. locking frequency modes ............................................................................................. .......................... 20 table 7-3. default i nput clock pr iorities ...................................................................................... .............................. 22 table 7-4. damping factors and peak jitter/ wander gain......................................................................... .............. 31 table 7-5. t0 dpll adaptation for t he t4 dpll phase me asurement mode .......................................................... 35 table 7-6. output clock capab ilities ........................................................................................... .............................. 37 table 7-7. digita l1 frequencies................................................................................................ ................................. 39 table 7-8. digita l2 frequencies................................................................................................ ................................. 39 table 7-9. apll frequency to out put frequencies (t0 apll and t4 apll) .......................................................... 40 table 7-10. t0 apll freq uency config uration .................................................................................... ..................... 40 table 7-11. t0 apll2 fre quency confi guration ................................................................................... .................... 40 table 7-12. t4 apll freq uency config uration .................................................................................... ..................... 41 table 7-13. oc1?oc7 out put frequency selection ................................................................................. ................ 41 table 7-14. standard frequencies for programm able outputs ...................................................................... .......... 42 table 7-15. external frame sync source ......................................................................................... ........................ 47 table 8-1. re gister map ........................................................................................................ .................................... 53 table 9-1. jtag in struction codes .............................................................................................. ........................... 119 table 9-2. jt ag id code ........................................................................................................ ................................ 120 table 10-1. recommended dc operating conditions ................................................................................ ............ 121 table 10-2. dc ch aracteristics................................................................................................. ............................... 121 table 10-3. cm os/ttl pins ...................................................................................................... ............................. 122 table 10-4. lvds/l vpecl input pins ............................................................................................. ....................... 122 table 10-5. lvds output pins ................................................................................................... ............................. 122 table 10-6. lvpecl level-c ompatible ou tput pins................................................................................ ............... 123 table 10-7. input clock timing................................................................................................. ............................... 125 table 10-8. input clock to output cl ock delay .................................................................................. ..................... 125 table 10-9. output clock phase ali gnment, frame sync alignment mode............................................................ 125 table 10-10. spi interface timing .............................................................................................. ............................. 126 table 10-11. jtag interface timing............................................................................................. ........................... 128 table 10-12. re set pin timing .................................................................................................. .............................. 129 table 11-1. pin assignment s sorted by signal name.............................................................................. ............... 130 table 12-1. csbga package thermal properties, natu ral convection ............................................................... .. 132
________________________________________________________________________________________ ds 3104-se 6 1. standards compliance table 1-1. applicable telecom standards specification specification title ansi t1.101 synchronization interface standard , 1999 tia/eia-644-a electrical characteristics of low voltage di fferential signaling (lvds) interface circuits, 2001 etsi en 300 417-6-1 transmission and multiplexing (tm); generic requirements of transport functionality of equipment; part 6-1: synchronization layer functions , v1.1.3 (1999-05) en 300 462-3-1 transmission and multiplexing (tm); generic requirements for synchronization networks; part 3-1: the control of jitter and wander within synchronization networks , v1.1.1 (1998-05) en 300 462-5-1 transmission and multiplexing (tm); generic requirements for synchronization networks; part 5-1: timing characteristics of slave clocks suitable for operation in synchronous digital hierarchy (sdh) equipment , v1.1.1 (1998-05) ieee ieee 1149.1 standard test access port and boundary-scan architecture , 1990 itu-t g.783 itu g.783 characteristics of synchronous digi tal hierarchy (sdh) equipment functional blocks (10/2000 plus amendment 1 06/2002 and corrigendum 2 03/2003) g.813 timing characteristics of sdh equipment slave clocks (sec) (03/2003) g.823 the control of jitter and wander within digital networks which are based on the 2048kbps hierarchy (03/2000) g.824 the control of jitter and wander within digital networks which are based on the 1544kbps hierarchy (03/2000) g.825 the control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (sdh) (03/2000) g.8261 timing and synchronization aspects in packet networks (05/2006, prepublished) g.8262 timing characteristics of synchronous ethernet equipment slave clock (eec) (06/2007, prepublished) telcordia gr-253-core sonet transport systems: common generic criteria , issue 3, september 2000 gr-378-core generic requirements for timing signal generators , issue 2, february 1999 gr-499-core transport systems generic requirements (tsgr) common requirements, issue 2, december 1998 gr-1244-core clocks for the synchronized ne twork: common generic criteria, issue 2, december 2000
________________________________________________________________________________________ ds 3104-se 7 2. application example figure 2-1. typical application example 4-port gigabit ethernet line card synchronization clock flow only. 10-gigabit and fast ethernet ports and sonet/sdh ports also supported. t4 dpll ic3 oc5 from sonet/sdh framers on the card (if any) to backplane and timing cards t0 dpll input clock selector, divider, monitor from master and slave timing cards ic1 ic2 input clock selector, divider, monitor oc1 19.44 mhz cmos/ttl oc2 oc3 oc4 gige phy gige mac rx_clk rx gmii tx gmii to gige optical components gige mac gige mac gige phy rx_clk rx gmii tx gmii to gige optical components gige phy rx_clk rx gmii tx gmii to gige optical components gige mac gige phy rx_clk rx gmii tx gmii to gige optical components ic4 ic8 ic9 125 mhz cmos/ttl holdover, phase build-out, frequency conversion frequency conversion DS3104-se
________________________________________________________________________________________ ds 3104-se 8 3. block diagram figure 3-1. DS3104-se functional diagram t0 dpll (filtering, holdover, hitless switching, frequency conversion) master clock generator oc4b oc5b oc6 pos/neg fsync mfsync ic3 ic4 ic5 pos/neg ic6 pos/neg ic8 ic9 microprocessor port (spi serial) and hw control and status pins local oscillator rst* cs cpha sclk sdi sdo intreq/srfail t4 dpll (frequency conversion) sonsdh srcsw refclk wdt jtag input clock selector, divider and monitor output clock synthesizer and selector (muxes, 7 dfs blocks, 3 aplls, output dividers) sync1 oc3b test gpio[4:1] srfail lock sync3 ic1 pos/neg ic2 pos/neg sync2 oc7 pos/neg oc5 pos/neg oc4 pos/neg oc2b oc1b oc4 oc5 oc3 oc2 oc1 cpol wdt jtrst* jtms jtclk jtdi jtdo pll bypass
________________________________________________________________________________________ ds 3104-se 9 4. detailed description figure 3-1 illustrates the blocks described in this secti on and how they relate to one another. section 5 provides a detailed feature list. the DS3104-se is a complete line card timing ic for system s with sonet/sdh or synchr onous ethernet ports. at the core of this device are two digital phase-locked loops (dplls) labeled t0 and t4 1 . dpll technology makes uses of digital-signal processing (dsp) and digital-frequenc y synthesis (dfs) techniques to implement plls that are precise, flexible, and have consistent performance over voltage, temperature, and manufacturing process variations. the DS3104-se?s dplls are digitally configur able for input and output frequencies, loop bandwidth, damping factor, pull-in/hold-in range, and a variety of other factors. both dplls can directly lock to many common telecom frequencies and also can lock at 8khz to any multiple of 8khz up to 156.25mhz. the dplls can also tolerate and filter significant amounts of jitter and wander. in typical line card applications, the t0 dpll takes re ference clock signals from two redundant system timing cards, monitors both, selects one and uses that reference to produce a variety of clocks that are needed to time the outgoing traffic interfaces of the line card (sonet/sdh, synchronous ethernet, etc.). to perform this role in a variety of systems with diverse perf ormance requirements, the t0 dpll has a sophisticated feature set and is highly configurable. t0 can automatically transition among free-run, locked and holdover states all without software intervention. in free-run, t0 generates a stable, low-noise clock with the same frequency accuracy as the external oscillator connected to the refclk pin. with software calibration t he DS3104-se can even im prove the accuracy to within 0.02ppm. when at least one input reference clock has been validated, t0 transitions to the locked state in which its output clock accuracy is equal to the accuracy of the input reference. while in the locked state, t0 acquires an average frequency value to use as the holdov er frequency. when its selected reference fails, t0 can very quickly detect the failure and enter the holdover state to avoid affecting its output clock. from holdover it can automatically switch to another input reference, again without affecting its output clock (hitless switching). switching among input references can be either revertive or nonrevertive. when all input references are lost, t0 stays in holdover in which it generates a stable low-noise cl ock with initial frequency accuracy equal to its stored holdover value and drift performance determined by the qualit y of the external oscillator. t0 can also perform phase build-outs and fine-granularity output clock phase adjustments. the t4 dpll has a much less demanding role to play and therefore is much simpler than t0. often t4 is used as a frequency converter to create a clock derived from one of the incoming traffic interfaces of the line card. this clock (often 19.44mhz, 38.88mhz, or 8khz) is sent across the system backplane to the system?s timing cards where a timing card ic creates a frequency-locked derived ds1- or e1-rate clock to be sent to a nearby bits timing signal generator (tsg, telcordia terminology) or sy nchronization supply unit (ssu, itu-t terminology) or uses it as the system clock reference in a line-timed mode of operation. in other applicat ions t4 is phase-locked to t0 and used as a frequency converter to produce additional output clock rates for use within the line card, such as nxds1, nxe1, nxds2, ds3, e3, 125mh z for synchronous gigabit ethernet, or 156.25mhz for synchronous 10g ethernet. t4 can also be configured as a measuring tool to measure the frequency of an input reference or the phase difference between two input references. at the front end of both the t0 and t4 dplls is the input clock selector, divi der, and monitor (icsdm) block. this block continuously monitors as many as 8 different input clocks of various frequencies for activity and frequency accuracy. in addition, icsdm maintains separate input cl ock priority tables for the t0 and t4 dplls and can automatically select and provide the hi ghest priority valid clock to each dpll without any software intervention. the icsdm block can also divide the selected clo ck down to a lower rate as needed by the dpll. the output clock synthesizer and selector (ocss) block shown in figure 3-1 and in more detail in figure 7-1 contains three output aplls?t0 apll, t0 apll2 and t4 apll?and their associated dfs engines and output divider logic plus several additional dfs engines. the apll dfs bl ocks do frequency tran slation, creating clocks 1 these names are adapted from output ports of the sets function s pecified in itu and etsi standards such as etsi en 300 462-2-1. although strictly speaking these names are appropriate only for timi ng card ics such as the ds3100 that can serve as the sets f unction, the names have been carried over to the DS3104-se so that all of t he products in maxim?s timing ic product line have consistent nom enclature.
________________________________________________________________________________________ ds 3104-se 10 of other frequencies that are phase/fr equency locked to the output clock of the associated dpll. the aplls multiply the clock rates from the apll dfs blocks and simu ltaneously attenuate jitter. altogether the output blocks of the DS3104-se can produce more than 90 different output frequencies including common sonet/sdh, pdh and synchronous ethernet rates plus 2khz and 8khz frame sync pulses. the entire chip is clocked from the external oscillat or connected to the refclk pin. thus the free-run and holdover stability of the DS3104-se is entirely a function of the stability of the external oscillator, the performance of which can be selected to match the application: xo or tcxo. the 12.8mhz clock from the external oscillator is multiplied by 16 by the master clock ge nerator block to create the 204.8mhz ma ster clock used by the rest of the device. since every block on the devic e depends on the master clock and ther efore the local oscillator clock for proper operation, the master clock generator has a watchdog timer (wdt) function that can be used to signal a local microprocessor in the event of a local oscillator clock failure.
________________________________________________________________________________________ ds 3104-se 11 5. detailed features 5.1 input clock features ? eight input clocks: four cmos/ttl ( 125mhz) and four lvds/lvpecl/cmos/ttl ( 156.25mhz) ? cmos/ttl input clocks accept any multiple of 2khz up to 125mhz ? lvds/lvpecl inputs accept any mult iple of 2khz up to 131.072mhz, any multiple of 8khz up to 155.52mhz plus 156.25mhz ? all input clocks are constantly monitored by programmable activity monitors ? fast activity monitor can disqualify the sele cted reference after two missing clock cycles ? three optional 2/4/8khz frame-sync in puts for frame-sync signals from master and slave timing cards and an optional backup timing source 5.2 timing card to line card dpll features (t0 dpll) ? high-resolution dpll plus two or three low-jitter output aplls ? sophisticated state machine autom atically transitions between free-run, locked, and holdover states ? revertive or nonrevertive reference selection algorithm ? programmable bandwidth from 0.1hz to 400hz ? separately configurable acquisition bandwidth and locked bandwidth ? programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 or 20 ? multiple phase detectors: phase/fr equency, early/late, and multicycle ? phase/frequency locking ( 360 capture) or nearest-edge phase locking ( 180 capture) ? multicycle phase detection and locking (up to 8191ui) improves jitter tolerance and lock time ? phase build-out in response to reference switching ? less than 5 ns output clock phase tr ansient during phase build-out ? output phase adjustment up to 200ns in 6ps steps with respect to selected input reference ? high-resolution frequency and phase measurement ? holdover frequency averaging over 1 second interval ? fast detection of input clock failure and transition to holdover mode ? low-jitter frame sync (8khz) and multiframe sync (2khz) aligned with output clocks 5.3 line card to timing card dpll features (t4 dpll) ? high-resolution dpll plus low-jitter output apll ? programmable bandwidth from 18hz to 70hz ? programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20 ? multiple phase detectors: phase/fr equency, early/late, and multicycle ? phase/frequency locking ( 360 capture) or nearest-edge phase locking ( 180 capture) ? multicycle phase detection and locking (up to 8191ui) improves jitter tolerance and lock time ? 2khz and 8khz frame syncs with programmable polarity and pulse width ? can operate independently or locked to t0 dpll ? phase detector can be used to measure phase difference between two input clocks ? optional pll bypass mode provides input clock monito ring, selection, and optional frequency division but bypasses the dpll and apll when they aren?t needed (e.g., dividing an input clock to 8khz) ? high-resolution frequency and phase measurement
________________________________________________________________________________________ ds 3104-se 12 5.4 output apll features ? three separate clock-multiplying, jitter attenuating aplls can simultaneously produce sonet/sdh rates, fast/gigabit ethernet rates and 10g ethernet rates, all locked to a common reference clock ? the t0 apll, always connected to the t0 dpll, ha s frequency options suitabl e for nx19.44mhz, nxds1, nxe1, nx25mhz and nx62.5mhz ? the t4 apll can be connected to either the t0 dpll or the t4 dpll and has frequency options suitable for nx19.44mhz, nxds1, nxe1, nxds2, ds3, e3 , nx10mhz, nx10.24mhz, nx13mhz, nx25mhz, and nx62.5mhz ? the t0 apll2, always connected to the t0 dpll, produces 312.5mhz for 10g synchronous ethernet applications 5.5 output clock features ? seven output clocks: three cmos/ttl ( 125mhz), two lvds/lvpecl ( 312.50mhz), and two dual cmos/ttl and lvds/lvpecl ? output clock rates include 2khz, 8khz, nxds1, nxe1, ds2, ds3, e3, 6.48mhz, 19.44mhz, 38.88mhz, 51.84mhz, 77.76mhz, 155.52mhz, 311.04mhz, 2. 5mhz, 25mhz, 125mhz, 156.25mhz, 312.50mhz, 10mhz, 10.24mhz, 13mhz, 30.72mhz and various mu ltiples and submultiples of these rates ? custom clock rates also available: any multiple of 2khz up to 77.76mhz and any multiple of 8khz up to 311.04mhz ? three independent output aplls support simultan eous generation of 155.52mhz for sonet/sdh, 125mhz for gigabit ethernet, and 156.25/312.5mhz for 10g et hernet (plus various multiples/submultiples of each) ? all outputs have < 1ns peak-to-peak output jitte r; outputs from aplls hav e < 0.5ns peak-to-peak ? each cmos/ttl clock output has two leads, the sta ndard output (e.g., oc1) with a 3.3v power supply, and the ?b? output (e.g., oc1b) conn ected to the vddiob power supply for optional 2.5v output signal levels. ? 8khz frame sync and 2khz multiframe sync outputs have programmable polarity and pulse width and can be disciplined by a 2khz or 8khz sync input 5.6 general features ? operates from a single external 12.80 0mhz local oscillator (xo or tcxo) ? on-chip watchdog circuit for the local (refclk) oscillator ? spi serial microprocessor interface ? four general-purpose i/o pins ? register set can be write-protected
________________________________________________________________________________________ ds 3104-se 13 6. pin descriptions table 6-1. input clo ck pin descriptions pin name (1) type (2) pin description refclk i reference clock. connect to a 12.800mhz, high-accuracy, high-stability, low-noise local oscillator (xo or tcxo). see section 7.3 . ic1pos, ic1neg i diff input clock 1. lvds/lvpecl or cmos/ttl. programma ble frequency (def ault 8khz). lvds/lvpecl: see table 10-4 , figure 10-1 and figure 10-2 . cmos/ttl: bias ic1neg to 1.4v and connect the single-ended signal to ic1pos. ic2pos, ic2neg i diff input clock 2. lvds/lvpecl or cmos/ttl. programma ble frequency ( default 8khz). lvds/lvpecl: see table 10-4 , figure 10-1 and figure 10-2 . cmos/ttl: bias ic2neg to 1.4v and connect the single-ended signal to ic2pos. this input can be associated with the sync3 pin. ic3 i pd input clock 3. cmos/ttl. programmable frequency (d efault 8khz). this input can be associated with the sync1 pin. ic4 i pd input clock 4. cmos/ttl. programmable frequency (d efault 8khz). this input can be associated with the sync2 pin. ic5pos, ic5neg i diff input clock 5. lvds/lvpecl or cmos/ttl. programma ble frequency (def ault 19.44mhz). lvds/lvpecl: see table 10-4 , figure 10-1 and figure 10-2 . cmos/ttl: bias ic5neg to 1.4v and connect the single-ended signal to ic5pos. this input can be associated with the sync1 pin. ic6pos, ic6neg i diff input clock 6. lvds/lvpecl or cmos/ttl. programma ble frequency (def ault 19.44mhz). lvds/lvpecl: see table 10-4 , figure 10-1 and figure 10-2 . cmos/ttl: bias ic6neg to 1.4v and connect the single-ended signal to ic6pos. this input can be associated with the sync2 pin. ic8 i pd input clock 8. cmos/ttl. programmable input re ference (default 19.44mhz). ic9 i pd input clock 9. cmos/ttl. programmable frequency (def ault 19.44mhz). this input can be associated with the sync3 pin. sync1 i pd frame sync1 input. 2khz, 4khz, or 8khz. fscr3 :source ! = 11xx this pin is the external frame sync inpu t associated with any input pin using the fscr3 :source field. fscr3 :source = 11xx this pin is the external frame sync signal associated with ic3 or ic5 depending on which one is currently selected and the setting of fscr1 .syncsrc[1:0]. sync2 i pd frame sync2 input. 2khz, 4khz, or 8khz. fscr3 :source ! = 11xx this pin is not used for the external frame sync signal. fscr3 :source = 11xx this pin is the external frame sync signal associated with ic4 or ic6 depending on which one is currently selected and the setting of fscr1 .syncsrc[1:0]. sync3 i pu frame sync3 input. 2khz, 4khz, or 8khz. fscr3 :source ! = 11xx this pin is not used for the external frame sync signal. fscr3 :source = 11xx this pin is the external frame sync signal associated with ic9 or ic2 depending on which one is currently selected and the setting of fscr1 .syncsrc[1:0].
________________________________________________________________________________________ ds 3104-se 14 table 6-2. output cl ock pin descriptions pin name (1) type (2) pin description oc1 o output clock 1. cmos/ttl. programmable frequency (default 25mhz) oc2 o output clock 2. cmos/ttl. programmable frequency (default 62.5mhz). oc3 o output clock 3. cmos/ttl. programmable frequency (default 77.76mhz) oc4 o output clock 4. cmos/ttl. programmable frequency (default 125mhz) oc5 o output clock 5. cmos/ttl. programmable frequency (default 155.52mhz). oc4pos, oc4neg o diff output clock 4. lvds/lvpecl. these pins present the same clock as the oc4 pin but in differential signal format. the output mode is selected by mcr8 .oc4sf[1:0]. see table 10-5 , table 10-6 , figure 10-1 , and figure 10-3. oc5pos, oc5neg o diff output clock 5. lvds/lvpecl. these pins present the same clock as the oc5 pin but in differential signal format. the output mode is selected by mcr8 .oc5sf[1:0]. see table 10-5 , table 10-6 , figure 10-1 , and figure 10-3. oc6pos, oc6neg o diff output clock 6. lvds/lvpecl. programmable frequency (default 156.25mhz lvds). the output mode is selected by mcr8 .oc6sf[1:0]. see table 10-5 , table 10-6 , figure 10-1 , and figure 10-3. oc7pos, oc7neg o diff output clock 7. lvds/lvpecl. programmable frequency (default 312.5mhz lvds). the output mode is selected by mcr8 .oc7sf[1:0]. see table 10-5 , table 10-6 , figure 10-1 , and figure 10-3. oc1b/ gpio1 o 3 output clock 1b/general-purpose io 1. cmos/ttl. (default clk1b, disabled) this pin is programmable as an output clock pin or a gpio pin using ocr6 .oc1ben. when programmed as a clock output pin (oc1ben = 1) it presents the same clock as the oc1 pin. this pin is powered from the vddiob power supply pin. oc2b/ gpio2 o 3 output clock 2b/general-purpose io 2. cmos/ttl. (default clk2b, disabled) this pin is programmable as an output clock pin or a gpio pin using ocr6 .oc2ben. when programmed as a clock output pin (oc2ben = 1) it presents the same clock as the oc2 pin. this pin is powered from the vddiob power supply pin. oc3b/ gpio3 o 3 output clock 3b/general-purpose io 3. cmos/ttl. (default clk3b, disabled) this pin is programmable as an output clock pin or a gpio pin using ocr6 .oc3ben. when programmed as a clock output pin (oc3ben = 1) it presents the same clock as the oc3 pin. this pin is powered from the vddiob power supply pin. oc4b o 3 output clock 4b. cmos/ttl (default off). when enabled ( ocr6 .oc4ben = 1), this pin presents the same clock as the oc4 pin. this pin is powered from the vddiob power pin. oc5b o 3 output clock 5b. cmos/ttl (default off) . when enabled ( ocr6 .oc5ben = 1), this pin presents the same clock as the oc5 pin. this pin is powered from the vddiob power pin. fsync o 3 fsync. cmos/ttl. 8khz frame sync or clock (defau lt 50% duty cycle clock, noninverted). the pulse polarity and width are selectable using fscr1 .8kinv and fscr1 .8kpul. mfsync o 3 mfsync. cmos/ttl. 2khz frame sync or clock (def ault 50% duty cycle clock, noninverted). the pulse polarity and width are selectable using fscr1 .2kinv and fscr1 .2kpul.
________________________________________________________________________________________ ds 3104-se 15 table 6-3. global pin descriptions pin name (1) type (2) pin description rst i pu reset (active low). when this global asynchronous reset is pulled low, all internal circuitry is reset to default values. the device is held in reset as long as rst is low. rst should be held low for at least two refclk cycles after the external oscillator has stabilized and is providing valid clock signals. srcsw i pd source switching. fast source-switching control input. see section 7.6.5 . the value of this pin is latched into mcr10 :extsw when rst goes high. after rst goes high this pin can be used to select between ic3/ic5 and ic4/ic6, if enabled. test i pd factory test mode select. wire this pin to v ss for normal operation. wdt i/o watchdog timer pin. analog node for the refclk watchdog timer. connect to a resistor (r) to v ddio and a capacitor (c) to ground. suggested values are r = 20k and c = 0.01 f. see section 7.3 . sonsdh/ gpio4 i/o pd sonet/sdh frequency select input or gpio4 pin. when rst goes high the state of this pin sets the reset-default state of mcr3 :sonsdh, mcr6 :dig1ss and mcr6 :dig2ss. after rst goes high this pin can be used as a general-purpose i/o pin. gpcr :gpio4d configures this pin as an input or an output. gpcr :gpio4o specifies the output value. gpsr :gpio4 indicates the state of the pin. reset latched values: 0 = sdh rates (n x 2.048mhz) 1 = sonet rates (n x 1.544mhz) srfail o srfail status. when mcr10 :srfpin = 1, this pin follows the state of the srfail latched status bit in the msr2 register. this gives the system a very fast indication of the failure of the current reference. when mcr10 :srfpin = 0, srfail is disabled (low). lock o t0 dpll lock status. when mcr1 .lockpin = 1, this pin indicates the lock state of the t0 dpll. when mcr1 .lockpin = 0, lock is disabled (low). 0 = not locked 1 = locked intreq/los o 3 interrupt request/loss of signal. programmable (default: intreq). the intcr :los bit determines whether the pin is indicates interrupt requests or loss of signal (i.e. loss of selected reference). intcr :los = 0: intreq mode the behavior of this pin is configured in the intcr register. polarity can be active high or active low. drive action can be push-pull or open drain. the pin can also be configured as a general-purpose output if the interru pt request function is not needed. intcr :los = 1: los mode this pin indicates the real-time state of the selected referenc e activity monitor (see section 7.5.3 ). this function is most useful when external switching mode (section 7.6.5 ) is enabled ( mcr10 :extsw = 1). table 6-4. spi bus m ode pin descriptions see section 7.10 for functional description and section 10.4 for timing specifications. pin name (1) type (2) pin description cs i pu chip select. this pin must be asserted (low) to read or write internal registers. sclk i serial clock. sclk is always driven by the spi bus master. sdi i serial data input. the spi bus master transmits dat a to the device on this pin. sdo o serial data output. the device transmits data to the spi bus master on this pin. cpha i clock phase. see figure 7-5 . 0 = data is latched on the leading edge of the sclk pulse. 1 = data is latched on the trailing edge of the sclk pulse. cpol i pd clock polarity. see figure 7-5 . 0 = sclk is normally low and pulses high during bus transactions. 1 = sclk is normally high and pulses low during bus transactions.
________________________________________________________________________________________ ds 3104-se 16 table 6-5. jtag inte rface pin descriptions see section 9 for functional description and section 10.5 for timing specifications. pin name (1) type (2) pin description jtrst i pu jtag test reset (active low). asynchronously resets the test access port (tap) controller. if not used, jtrst can be held low or high. jtclk i jtag clock. shifts data into jtdi on the rising edge and out of jtdo on the falling edge. if not used, jtclk can be held low or high. jtdi i pu jtag test data input. test instructions and data are clock ed in on this pin on the rising edge of jtclk. if not used, jtdi can be held low or high. jtdo o 3 jtag test data output. test instructions and data are clo cked out on this pin on the falling edge of jtclk. if not used, leave floating. jtms i pu jtag test mode select. sampled on the rising edge of jtclk and is used to place the port into the various defined ieee 114 9.1 states. if not used connect to vddio or leave floating. table 6-6. power-su pply pin descriptions pin name (1) type (2) pin description vdd p core power supply. 1.8v 10%. vddio p i/o power supply. 3.3v 5%. vddiob p power for pins oc1b through oc5b. voltage can be from 2.5v 5% to 3.3v 5%. vss p ground reference vdd_oc45 p power supply for differential outp uts oc4pos/neg and oc5pos/neg. 1.8v 10%. vss_oc45 p return for differenti al outputs oc4pos/neg and oc5pos/neg vdd_oc67 p power supply for differential outp uts oc6pos/neg and oc7pos/neg. 1.8v 10%. vss_oc67 p return for lvds differential out puts oc6pos/neg and oc7pos/neg avdd_pll1 p power supply for master clock generator apll. 1.8v 10%. avss_pll1 p return for master clock generator apll avdd_pll2 p power supply for t0 apll. 1.8v 10%. avss_pll2 p return for t0 apll avdd_pll3 p power supply for t4 apll. 1.8v 10%. avss_pll3 p return for t4 apll avdd_pll4 p power supply for t0 apll2. 1.8v 10%. avss_pll4 p return for t0 apll2 note 1: all pin names with an overbar (e.g., rst ) are active low. note 2: all pins, except power and analog pi ns, are cmos/ttl unless otherwise specified in the pin description. pin types i = input pin i diff = input pin that is lvds/lvpecl differential signal compatible i pd = input pin with internal 50k pulldown i pu = input pin with internal 50k pullup i/o = input/output pin io pd = input/output pin with internal 50k pulldown io pu = input/output pin with internal 50k pullup o = output pin o 3 = output pin that can tri-stated (i.e., placed in a high-impedance state) o diff = output pin that is lvds/lvpecl differential signal compatible p = power-supply pin note 3: all digital pins, except ocn, are i/o pins in jtag mode. ocn pins do not have jtag functionality.
________________________________________________________________________________________ ds 3104-se 17 7. functional description 7.1 overview the DS3104-se has eight input clocks pins and three fram e-sync input pins. the devic e can output as many as nine different clock frequencies on 16 output clock pins. th ere are two separate dplls in the device: the high- performance t0 dpll and the simpler the t4 dp ll. both dplls can generate output clocks. see figure 3-1 . four of the input clock pins are single-ended and can accept clock signals from 2khz to 125mhz. the other four are differential inputs that can accept clock signals up to 156.25mhz. the differential inputs can be configured to accept differential lvds or lvpecl signals or single-ended cmos/ttl signals. each input clock can be monitored continually for activi ty, and each can be marked unavailable or given a priority number. separate input priority numbers are maintained for the t0 dpll and the t4 dpll. except in special modes, the highest priority valid input is automatically selected as the reference for each path. srfail is set or cleared based on activity and/or frequency of the selected input. both the t0 dpll and the t4 dpll can directly lock to many common telecom and datacom frequencies, including, but not limited to 8khz, ds1, e1, 10mhz, 19.44mhz, and 38.88mhz as well as ethernet frequencies including 25mhz, 62.5mhz, 125mhz and 156.25mhz. the dplls can also lock to multiples of the standard direct- lock frequencies including 8khz. the t0 dpll is the high-performance path with all the features needed for synchronizing a line card to dual redundant system timing card s. the t4 dpll is a simple r auxiliary path typically used to provide a clock derived from an incoming line rate to system timing cards. the t4 apll can be connected to either the t4 dpll or the t0 dpll to provide more low-jitter output frequencies from the t0 dpll. there is also a dedicated low-jitter apll output that operates at 312.5mhz for 10g ethernet applications. using the optional pll bypass, the t4 selected reference, after any frequency division, can be directly output on any of the oc1 to oc7 output clock pins. both dplls have these features: ? automatic reference selection based on input activity and priority ? optional manual reference selection/forcing ? adjustable pll characteristics, including bandwidth, pull-in range, and damping factor ? ability to lock to several common telecom and ethernet frequencies plus multiples of any standard direct lock frequency. ? frequency conversion between input and out put using digital frequency synthesis ? combined performance of a stable, consistent digital pll and low-jitter analog output plls the t0 dpll has these additional feat ures not available in the t4 dpll: ? a full state machine for automatic transitions among free-run, locked, and holdover states ? nonrevertive reference switching mode ? phase build-out for reference switching (?hitless?) ? output vs. input phase offset control ? 13 bandwidth selections from 0.1hz to 400hz (vs. six selections for the t4 dpll) ? noise rejection circuitry for low-frequency references ? output phase alignment to input frame sync signal ? instant digital one-second averaging and free-run holdover modes the t4 dpll has these additional feat ures not available in the t0 dpll: ? three bandwidth selections limited to 18hz to 70hz ? optional mode to measure the phase difference between two input clocks
________________________________________________________________________________________ ds 3104-se 18 typically, the internal state machine controls the t0 dpll, but manual control by system software is also available. the t4 dpll has a simpler state machine that software cannot directly control. in either dpll, however, software can override the dpll logic using manual reference selection. the output and feedback synthesizers are locked to either t he t0 dpll or the t4 dpll. most of the output signals that are locked to the same dpll are always aligned to the falling edge at 2khz. the outputs of the t0 dpll and the t4 dpll can be connected to seven output dfs engines. see figure 7-1 . three of these output dfs engines are associated with hi gh-speed aplls that multiply the dpll clock rate and filter dpll output jitter. the outputs of the aplls are divided down to make a wide variety of possible frequencies available at the output clock pins. t0 apll and t0 apll2 are always locked to the t0 dpll, while the t4 apll can lock to either the t4 dpll or the t0 dpll. the out put frequencies from the t0 dpll can be synchronized to an input 2, 4, or 8khz sync signal (sync1, sync2, or sync3 input pins). the oc1 to oc7 output clocks can be configured for a va riety of different frequencies that are frequency and phase locked to either the t0 dpll or the t4 dpll. the oc6 and oc7 outputs are lvds/lvpecl, oc4 and oc5 are available in both lvds/lvpecl and 3.3v cmos, oc1 to oc3 are 3.3v cmos. there are five outputs oc1b to oc5b that can be 3.3v or 2.5v cmos outputs. al together more than 60 output frequencies are possible, ranging from 2khz to 312.5mhz. the fsync output clock is always 8khz, and the mfsync output clock is always 2khz. 7.2 device identification and protection the 16-bit read-only id field in the id1 and id2 registers is set to 0c20h = 3104 decimal. the device revision can be read from the rev register. contact the factory to interpret th is value and determine the latest revision. the register set can be protected from inadvertent writes using the prot register. 7.3 local oscillator and master clock configuration the t0 dpll, the t4 dpll and the output dfs engines operate from a 204. 8mhz master clock. the master clock is synthesized from a 12.800m hz clock originating from a local oscillator attached to the refclk pin. the stability of the t0 dpll in free-run or holdover is equivalent to the stabilit y of the local oscillator. selection of an appropriate local oscillator is therefore of crucial importance if the telecom standards listed in table 1-1 are to be met. simple xos can be used in less stringent cases, but tcxos or even ocxos may be required in the most demanding applications. careful evaluation of the local oscillator co mponent is necessary to ensure proper performance. contact maxim at telecom.support@dalsemi.com for recommended oscillators. the stability of the local oscillator is very important, but its absolute frequency accuracy is less important because the dplls can compensate for frequency inaccuracies when synthesizing the 204.8mhz master clock from the local oscillator clock. the mc lkfreq field in registers mclk1 and mclk2 specifies the frequency adjustment to be applied. the adjust can be from -771ppm to +514ppm in 0.0196229ppm (i.e., ~0.02ppm) steps. the DS3104-se has a watchd og circuit that causes an interrupt on t he intreq pin when the local oscillator attached to the refclk pin is significantly off frequency. the watchdog interrupt is not maskable, but is subject to the intcr register settings. when the watchdog circuit activate s, reads of any and all registers in the device will return 00h to indicate the failure. in response to the activation of the intreq pin or during periodic polling, if system software ever reads 00h from the id registers (which are hard-coded to 0c20h = 3104 decimal) then it can conclude that the local oscillator attached to that DS3104-se has failed. for proper operation of the watchdog timer, connect the wdt pin to a 10k resistor (r) to vddio and a 0.01 f capacitor (c) to vss.
________________________________________________________________________________________ ds 3104-se 19 7.4 input clock configuration the DS3104-se has eight input clocks, ic1 to ic6 and ic8 and ic9. table 7-1 provides summary information about each clock, including signal format and available frequen cies. the device tolerates a wide range of duty cycles on input clocks, out to a minimum high time or minimum low time of 3ns or 30% of the clock period, whichever is smaller. 7.4.1 signal format configuration inputs with cmos/ttl signal format ac cept both ttl and 3.3v cmos levels. one key configuration bit that affects the available frequencies is the sonsdh bit in mcr3 . when sonsdh = 1 (sonet mode), the 1.544mhz frequency is available. when sonsdh = 0 (sdh mode), the 2.048mhz frequency is available. during reset the default value of this bit is latched from the sonsdh pin. input clocks ic1, ic2, ic5, and ic6 can be configured to accept lvds, l vpecl, or cmos/ttl signals by using the proper set of external components. th e recommended lvds termination is shown in figure 10-1 while the recommended lvpecl termi nation is shown in figure 10-2 . the electrical specifications for these inputs are listed in table 10-4 . to configure these differential inputs to ac cept single-ended cmos/ttl signals, use a voltage- divider to bias the icxneg pin to approximately 1.4v and connect the single-ended signal to the icxpos pin. if a differential input is not used it should be configured left floating (one input is internally pulled high and the other internally pulled low). (see also mcr5 :ic5sf and ic6sf.) table 7-1. input clock capabilities input clock signal formats frequencies (mhz) default frequency ic1 lvds/lvpecl or cmos/ttl up to 156.25 (2) 8khz ic2 lvds/lvpecl or cmos/ttl up to 156.25 (2) 8khz ic3 cmos/ttl up to 125 (1) 8khz ic4 cmos/ttl up to 125 (1) 8khz ic5 lvds/lvpecl or cmos/ttl up to 156.25 (2) 19.44mhz ic6 lvds/lvpecl or cmos/ttl up to 156.25 (2) 19.44mhz ic8 cmos/ttl up to 125 (1) 19.44mhz ic9 cmos/ttl up to 125 (1) 19.44mhz note 1: available frequencies for cmos/ttl input clocks are: 2khz, 4khz, 8khz, 1.544mhz (sonet mode), 2.048mhz (sdh mode), 6.312mhz, 6.48mhz, 19.44mhz, 25.0mhz, 25.92mhz, 38.88mhz, 51.84mhz, 62.5mhz, 77.76mhz, and any multiple of 2khz up to 125mhz. note 2: available frequencies for lvds/lvpecl input clo cks include all cmos/ttl frequencies in note 1 plus any multiple of 8khz up to 155.52mhz and 156.25mhz.
________________________________________________________________________________________ ds 3104-se 20 7.4.2 frequency configuration input clock frequencies are configured in the freq field of the icr registers. the divn a nd lock8k bits of these same registers specify the locking frequency mode, as shown in table 7-2 . table 7-2. locking frequency modes divn lock8k locking frequency mode 0 0 direct lock 0 1 lock8k 1 0 divn 1 1 alternate direct lock 7.4.2.1 direct lock mode in direct lock mode, the dplls lock to the selected re ference at the frequency specified in the corresponding icr register. direct lock mode can only be used for input cl ocks with these specific fr equencies: 2khz, 4khz, 8khz, 1.544mhz, 2.048mhz, 5mhz, 6.312mhz, 6.48mhz, 19 .44mhz, 25.92mhz, 31.25mhz, 38.88mhz, 51.84mhz, 77.76mhz, and 155.52mhz. for the 155.52mhz case, the inpu t clock is internally divided by two, and the dpll direct-locks at 77.76mhz. the divn mode can be used to divi de an input down to any of these frequencies except 155.52mhz. mtie figures may be marginally better in direct lock mode because the higher frequencies allow more frequent phase updates. 7.4.2.2 alternate direct lock mode alternate direct lock mode is the same as direct lock mode except an alternate list of di rect lock frequencies is used (see the freq field definition in the icr register description). the alternat e frequencies are included to support clock rates found in ethernet, cmts, wireless, and g ps applications. the alternate frequencies are: 10mhz, 25mhz, 62.5mhz, 125mhz, and 156.25mhz. the frequencies 62.5mhz, 125mhz, and 156.25mhz are internally divided down to 31.25mhz, while 10mhz and 25mhz are internally divided down to 5mhz. 7.4.2.3 lock8k mode in lock8k mode, an internal divider is configured to divide the selected reference down to 8khz. the dpll locks to the 8khz output of the divider. lock8k mode can only be used for input clocks with the standard direct lock frequencies: 8khz, 1.544mhz, 2.048mhz, 5mhz, 6.312mhz, 6.48mhz, 19.44mhz, 25.0mhz, 25.92mhz, 31.25mhz, 38.88mhz, 51.84mhz, 62.5mhz, 77.76mhz, and 155.52mhz. lock8k mode is enabled for a particular input clock by setting the lock 8k bit in the corresponding icr register. lock8k mode cannot be used with 5mhz input clocks. lock8k mode gives a greater tolerance to input jitter when the multicycle phase detector is disabled because it uses lower frequencies for phase comparisons. the cloc k edge to lock to on the selected reference can be configured using the 8kpol bit in the test1 register. for 2khz and 4khz clocks the lock8k bit is ignored and direct-lock mode is used. 7.4.2.4 divn mode in divn mode, an internal divider is configured from the value stored in the divn registers. the divn value must be chosen so that when the selected reference is divided by divn+1, the resulting clock frequency is the same as the standard direct lock frequency selected in the freq field of the icr register. the dpll locks to the output of the divider. divn mode can only be used for input clocks whose frequency is less than or equal to 155.52mhz. the divn register field can range from 0 to 65,535 inclusive. the same divn+1 factor is used for all input clocks configured for divn mode. note that although the divn divider is able to divide down clock rates as high as 155.52mhz, the cmos/ttl inputs are only rat ed for a maximum clock rate of 125mhz.
________________________________________________________________________________________ ds 3104-se 21 7.5 input clock monitoring each input clock is continuously monitored for activity. activity monitoring is described in sections 7.5.2 and 7.5.3 . the valid/invalid state of each input clock is reported in the corresponding real-tim e status bit in registers valsr1 or valsr2 . when the valid/invalid state of a clock changes, the corresponding latched status bit is set in registers msr1 or msr2 , and an interrupt request occurs if the corres ponding interrupt enable bit is set in registers ier1 or ier2 . input clocks marked invalid cannot be automatically selected as the reference for either dpll. if the t4 dpll does not have any valid input clocks availabl e, the t4noin status bit is set to 1 in msr3 . 7.5.1 frequency monitoring the DS3104-se monitors the frequency of each input clock and invalidates any clock whose frequency is more than 10,000ppm away from nominal. the frequency range monitor can be disabled by clearing the mcr1 .fren bit. the frequency range measurement uses the internal 204.8mhz master clock as the frequency reference. 7.5.2 activity monitoring each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. a leaky bucket accumulator is similar to an analog integrator: the out put amplitude increases in the presence of input events and gradually decays in the absence of events. when event s occur infrequently, the accumulator value decays fully between events and no alarm is declared. when events occu r close enough together, the accumulator increments faster than it can decay and eventually reaches the alarm threshold. after an alarm has been declared, if events occur infrequently enough, the accumulator can decay fast er than it is incremented and eventually reaches the alarm clear threshold. the leaky bucket events come from the frequency range and fast activity monitors. the leaky bucket accumulator for each input clock can be as signed one of four configurations (0 through 3) in the bucket field of the icr registers. each leaky bucket configuration has programmable size, alarm declare threshold, alarm clear threshold, and decay rate, all of which are specified in the lbxy registers. activity monitoring is divided into 128ms intervals. the ac cumulator is incremented once for each 128ms interval in which the input clock is inactive for more than two cycles (more than four cycles for 155.52mhz, 156.25mhz, 125mhz, 62.5mhz, 25mhz and 10mhz input clocks). thus the ?f ill? rate of the bucket is at most 1 unit per 128ms, or approximately 8 units/second. during each period of 1, 2, 4 or 8 intervals (programmable), the accumulator decrements if no irregularities occur. thus the ?leak? rate of the bucket is approximately 8, 4, 2, or 1 units/second. a leak is prevented when a fill event occurs in the same interval. when the value of an accumulator reaches the alarm threshold ( lbxu register), the corresponding act alarm bit is set to 1 in the 4 isr registers, and the clock is marked invalid in the valsr registers. when the value of an accumulator reaches the alarm clear threshold ( lbxl register), the activity alarm is cleared by clearing the clock?s act bit. the accumulator cannot increment past the size of the bucket specified in the lbxs register. the decay rate of the accumulator is specified in the lbxd register. the values stored in the leaky bucket configuration registers must have the following relationship at all times: lbxs lbxu > lbxl . when the leaky bucket is empty, the minimum time to decl are an activity alarm in seconds is lbxu / 8 (where the ?x? in ?lbxu? is the leaky bucket conf iguration number, 0 to 3). the minimum time to clear an activity alarm in seconds is 2^lbxd x (lbxs ? lbxl) / 8. as an example, as sume lbxu = 8, lbxl = 1, lbxs = 10, and lbxd = 0. the minimum time to declare an activity alarm would be 8 / 8 = 1 second. the minimum time to clear the activity alarm would be 2^0 x (10 ? 1) / 8 = 1.125 seconds. 7.5.3 selected reference activity monitoring the input clock that each dpll is cu rrently locked to is called the select ed reference. the quality of a dpll?s selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference can cause unwanted jitter, wander or frequency offset on the output clocks. when anomalies occur on the selected reference they must be detected as soon as possible to give the dpll opportunity to temporarily disconnect from the reference until the reference is available again. by design, the regular input clock activity monitor (section
________________________________________________________________________________________ ds 3104-se 22 7.5.2 ) is too slow to be suitable for monitoring the selected reference. instead, each dpll has its own fast activity monitor that detects that the frequency is within ran ge (approximately 10,000ppm) and detects inactivity within approximately two missing reference cl ock cycles (approximately four miss ing cycles for 156.25mhz, 155.52mhz, 125mhz, 62.5mhz, 25mhz, and 10mhz references). when the t0 dpll detects a no-activity event, it immediat ely enters mini-holdover mode to isolate itself from the selected reference and sets the srfail bit in msr2 . the setting of the srfail bit can cause an interrupt request if the corresponding enable bit is set in ier2 . if mcr10 :srfpin = 1, the srfail output pin follows the state of the srfail status bit. optionally, a no-activity event can al so cause an ultra-fast reference switch (see section 7.6.4 ). when phlim1 :nalol = 0 (default), the t0 dpll does not decl are loss-of-lock during no-activity events. if the selected reference becomes available again before any alarms are declared by the activity monitor, then the t0 dpll continues to track the selected reference using nearest-edge locking ( 180 ) to avoid cycle slips. when nalol = 1, the t0 dpll declares loss-of-lock during no-ac tivity events. this causes the t0 dpll state machine to transition to the loss-of-lock state, which sets the msr2 :state bit and causes an interrupt request if enabled. if the selected reference becomes available again before any alar ms are declared by the activi ty monitor, then the t0 dpll tracks the selected reference using phase/frequency locking ( 360 ) until phase lock is reestablished. when the t4 dpll detects a no-activity event, its behav ior is similar to the t0 dpll with respect to the phlim1 :nalol control bit. unlike the t0 dpll, however, t he t4 dpll does not set the srfail status bit. if nalol = 1, the t4 dpll clears the opstate :t4lock status bit, which sets msr3 :t4lock and causes an interrupt request if enabled. 7.6 input clock priority, selection and switching 7.6.1 priority configuration during normal operation, the selected reference for t he t0 dpll and the selected reference for the t4 dpll are chosen automatically based on the priori ty rankings assigned to the input cloc ks in the input priority registers ( ipr1 to ipr5 ). each of these registers has priority fields fo r one or two input clocks. when t4t0 = 0 in the mcr11 register, the ipr registers specify the input clock prioriti es for the t0 dpll. when t4t0 = 1, the ipr registers specify the input clock priorities for the t4 dpll. the def ault input clock priorities, for both plls, are shown in table 7-3 . any unused input clock should be given the priority value 0, which disables the clock and marks it as unavailable for selection. priority 1 is highest while priority 15 is lowest. the same priority can be given to two or more clocks. table 7-3. default in put clock priorities input clock t0 dpll default priority t4 dpll default priority ic1 0 (off) 0 (off) ic2 1 1 ic3 2 2 ic4 3 3 ic5 0 (off) 0 (off) ic6 0 (off) 0 (off) ic8 4 5 ic9 5 0 (off) 7.6.2 automatic selection algorithm the real-time valid/invalid state of eac h input clock is maintained in the valsr1 and valsr2 registers. the selected reference can be marked invalid for phase lock , frequency, or activity. other input clocks can be invalidated for frequency or activity.
________________________________________________________________________________________ ds 3104-se 23 the reference selection algorithm for each dpll chooses t he highest-priority valid input clock to be the selected reference. to select the proper input cl ock based on these criteria, the selection algorithm maintains a priority table of valid inputs. the top three entries in this t able and the selected reference are displayed in the ptab1 and ptab2 registers. when t4t0 = 0 in the mcr11 register, these registers indicate the highest priority input clocks for the t0 dpll. when t4t0 = 1, they indicate t he highest priority input clocks for the t4 dpll. if two or more input clocks are given the same priority number then those inputs are pr ioritized among themselves using a fixed circular list. if one equal-priority clock is the selected reference but becomes invalid then the next equal-priority clock in the list becomes the selected refere nce. if an equal-priority clock that is not the selected reference becomes invalid, it is simply skipped over in t he circular list. the selection among equal-priority inputs is inherently nonrevertive, and revertive switching mode (s ee next paragraph) has no effect in the case where multiple equal-priority inputs have the highest priority. an important input to the selection algorith m for the t0 dpll is the revert bit in the mcr3 register. in revertive mode (revert = 1), if an input clock with a higher priority than the selected reference becomes valid, the higher priority reference immediat ely becomes the selected reference. in nonrevertive mode (revert = 0), the higher priority reference does not immediately become the sele cted reference but does become the highest priority reference in the priority table (ref1 field in the ptab1 register). (the selection algorithm always switches to the highest-priority valid input when the se lected reference goes invalid, regard less of the state of the revert bit.) for many applications, nonrevertive mode is preferred fo r the t0 dpll because it minimizes disturbances on the output clocks due to reference switching. the t4 dpll always operates in revertive mode. in nonrevertive mode, planned switchover to a newly-valid higher priority input clock can be done manually under software control. the validation of the new higher pr iority clock sets the corre sponding status bit in the msr1 or msr2 register, which can drive an interrupt request on the intreq pin if needed. system software can then respond to this change of state by briefly enabling re vertive mode (toggling revert high then back low) to drive the switchover to the higher priority clock. 7.6.3 forced selection the t0force field in the mcr2 register and the t4force field in the mcr4 register provide a way to force a specified input clock to be the selected reference for the t0 and t4 dplls, respectively. in both t0force and t4force, values of 0 and 15 specify normal operation with automatic reference selection. values from 1 to 6 and 8 and 9 specify the input clock to be the forced selection; other values will cause no input to be selected. internally, forcing is accomplished by giving the specified clock the highest priority (as specified in ptab1 :ref1). in revertive mode ( mcr3 :revert = 1) the forced clock automatically beco mes the selected reference (as specified in ptab1 :selref) as well. in nonrevertive mode (t0 dpll only) the forced clock only becomes the selected reference when the existing selected reference is invali dated or made unavailable for selection. in both revertive and nonrevertive modes when an input is forced to be the highest priority, the normal highest priority input (when no input is forced) is listed as the second-highest priority ( ptab2 :ref2) and the normal second-highest priority input is listed as the third-highest priority ( ptab2 :ref3). when the t4 dpll is used to measure the phase differe nce between the t0 dpll selected reference and another reference input by setting the t0cr1 :t4mt0 bit, the t4force field in the mcr4 register can be used to select the other reference input. 7.6.4 ultra-fast reference switching by default, disqualification of the select ed reference and switchover to another reference occurs when the activity monitor?s inactivity alarm threshold has been crossed, a process that takes on the order of hundreds of milliseconds or seconds. for the t0 dpll, an option for extremely fast disqualificat ion and switchover is also available. when ultra-fast switching is enabled ( mcr10 :ufsw = 1), if the fast activity monitor detects approximately two missing clock cycles it declares the refe rence failed by forcing the leaky bucket accumulator to its upper threshold (see section 7.5.2 ) and initiates reference switching. this is in addition to setting the srfail bit in msr2 and optionally generating an interrupt request, as described in section 7.5.3 . when ultra-fast switching occurs, the t0 dpll transitions to the prelocked 2 state, which allows switching to occur faster by bypassing the loss-of-lock state. the device should be in nonrevertive m ode when ultra-fast switching is enabled. if the device is
________________________________________________________________________________________ ds 3104-se 24 in revertive mode, ultra-fast switching could cause excessi ve reference switching when the highest priority input is intermittent. 7.6.5 external reference switching mode in this mode the srcsw input pin controls reference swit ching between two clock inputs. this mode is enabled by setting the extsw bit to 1 in the mcr10 register. in this mode, if the srcsw pin is high, the t0 dpll is forced to lock to input ic3 (if the priority of ic3 is nonzero in ipr2 ) or ic5 (if the priority of ic3 is zero) whether or not the selected input has a valid reference signal. if the srcsw pi n is low the t0 dpll is forced to lock to input ic4 (if the priority of ic4 is nonzero in ipr2 ) or ic6 (if the priority of ic4 is zero) whether or not the selected input has a valid reference signal. during reset the default value of the extsw bit is latched from the srcsw pin. if external reference switching mode is enabled during reset, the default frequency tolerance ( dlimit registers) is configured to 80ppm rather than the normal default of 9.2ppm. in external reference switching mode the device is simply a clock switch, and the t0 dpll is forced to lock onto the selected reference whether it is valid or not. unlike forced reference selection (section 7.6.3 ) this mode controls the ptab1 :selref field directly and is, therefor e, not affected by the state of the mcr3 :revert bit. during external reference switching mode, only ptab1 :selref is affected; the ref1, ref2, and ref3 fields in the ptab registers continue to indicate the highest, second-highes t, and third-highest priority valid inputs chosen by the automatic selection logic. external refer ence switching mode only affects the t0 dpll. 7.6.6 output clock phase conti nuity during reference switching if phase build-out is enabled (pboen = 1 in mcr10 ) or the dpll frequency limit ( dlimit ) is set to less than 30ppm, the device always complies with the gr-1244-core requirement that the rate of phase change must be less than 81ns per 1.326ms during reference switching.
________________________________________________________________________________________ ds 3104-se 25 7.7 dpll architecture and configuration both t0 and t4 are digital plls with separate analog plls (aplls) as the output stage. this architecture combines the benefits of both pll types. see figure 7-1 . figure 7-1. dpll block diagram t0 dpll t4 dpll locking frequency t0 pfd and loop filter t0 foward dfs t0 feedback dfs dig12 dfs t0 selected reference oc1, oc2, oc3, oc4, oc5, oc6, oc7 t4 foward dfs t4 feedback dfs t4 pfd and loop filter locking frequency t4 selected reference t0cr1:t0freq[2:0] ocrm:ofreqn[3:0] ocr5:aofn t0cr1:t4apt0 t0cr1:lkt4t0 t0cr1:t4mt0 t4cr1:t4freq[3:0] t0cr1:t0ft4[2:0] fscr1:2k8ksrc t0cr1:lkt4t0 1 0 apll output dividers t0 output apll t0 apll dfs apll output dividers t4 output apll t4 apll dfs dig12 dfs 2k8k dfs mcr6:dig2ss mcr6:dig2f[1:0] mcr6:dig2af mcr6:dig1ss mcr6:dig1f[1:0] mcr7:dig1src t0cr1:lkt4t0 mcr7:dig2src t0cr1:lkt4t0 output dfs fsync dfs sync2k sync2k fscr2:indep dig2 dig1 2k8k icrn:freq[3:0] icrn:freq[3:0] apll output dividers t0 output apll2 t0 apll2 dfs 2 2 fsync, mfsync ocr4:fsen, mfsen fscr1:8kinv, 2kinv fscr1:8kpol, 2kpol pll bypass digital plls have two key benefits: (1) stable, repeatable perform ance that is insensitive to process variations, temperature, and voltage; and (2) flexible behavior that is easily programmed via configuration registers. dplls use digital frequency synthesis (dfs) to generate various clocks. in dfs a hi gh-speed master clock (204.8mhz) is multiplied up from the 12.800mhz local oscillator clock applie d to the refclk pin. this master clock is then digitally divided down to the desired output frequency. the dfs output clock has jitter of about 1ns pk-pk.
________________________________________________________________________________________ ds 3104-se 26 the analog plls filter the jitter from the dplls, reduci ng the 1ns pk-pk jitter to less than 0.5ns pk-pk and 60ps rms, typical, measured broadband (10hz to 1ghz). the dplls in the device are configurable for many p ll parameters including bandwidth, damping factor, input frequency, pull-in/hold-in range, input-to-output phase o ffset, phase build-out, and more. no knowledge of loop equations or gain parameters is required to configur e and operate the device. no external components are required for the dplls or the aplls ex cept the high-quality local oscillator connected to the refclk pin. the t0 dpll to t0 apll path is the main path th rough the device. the t0 dpll has a full free- run/locked/holdover state machine and full programmability. the t4 dpll to t4 apll path is a simpler frequency converter/synthesis path, lacking the low bandwidth setting s, phase build-out, and phase adjustment controls found in the t0 dpll. 7.7.1 t0 dpll state machine the t0 dpll has three main timing modes: locked, holdover and free-run. the control state machine for the t0 dpll has states for each timing mode as well as three te mporary states: prelocked, prelocked 2 and loss-of-lock. the state transition diagram is shown in figure 7-2 . descriptions of each state are given in the paragraphs below. during normal operation the state machine controls state transitions. when necessary, however, the state can be forced using the t0state field of the mcr1 register. whenever the t0 dpll changes state, the state bit in msr2 is set, which can cause an interrupt request if enabled. the current t0 dpll state can be read from the t0state field of the opstate register. 7.7.1.1 free-run state free-run mode is the reset default state. in free-run a ll output clocks are derived from the 12.800 mhz local oscillator attached to the refclk pin. the frequency of each ou tput clock is a specific multiple of the local oscillator. the frequency accuracy of each output clo ck is equal to the frequency ac curacy of the master clock, which can be calibrated using the mclkfreq field in registers mclk1 and mclk2 (see section 7.3 ). the state machine transitions from free-run to the prelock ed state when at least one input clock is valid. 7.7.1.2 prelocked state the prelocked state provides a 100 -second period (default value of phlkto register) for the dpll to lock to the selected reference. if phase lock (see section 7.7.6 ) is achieved for 2 seconds dur ing this period then the state machine transitions to locked mode. if the dpll fails to lock to the selected reference within the phase-lock timeout period specified by phlkto then a phase lock alarm is raised (corresponding lock bit set in the isr register), invalidating the input (icn bit goes low in valsr registers). if another input clock is valid then the st ate machine re-enters the prelocked state and tries to lock to the alternate input clock. if no other input cloc ks are valid for two seconds, then the state machine transitions back to the free-run state. in revertive mode (revert = 1 in mcr3 ), if a higher priority input clock becomes valid during the phase-lock timeout period then the state machine re -enters the prelocked state and tries to lock the higher priority input. if a phase-lock timeout period longer than 100 seconds is required for locking, then the phlkto register must be configured accordingly.
________________________________________________________________________________________ ds 3104-se 27 figure 7-2. t0 dpll state transition diagram free-run select ref (001) pre-locked wait for <=100s (110) reset all input clo cks evaluated at least one input valid (selected reference invalid > 2s or out of lock >100s) and no valid input clock locked (100) phase-locked to selected reference > 2s loss-of-lock wait for <=100s (111) holdover select ref (010) loss-of-lock on selected reference phase-lock regained on selected reference within 100s pre-locked 2 wait for <=100s (101) (selected reference invalid > 2s or out of lock >100s) and no valid input clock available [selected reference invalid or (revertive mode and valid higher-priority input) or out of lock >100s] and valid input clock available [selected reference invalid or out of lock >100s or (revertive mode and valid higher-priority input)] and valid input clock available [selected reference invalid or out of lock >100s or (revertive mode and valid higher-priority input)] and valid input clock available (selected reference invalid > 2s or out of lock >100s) and no valid input clock available all input clo cks evaluated at least one input valid selected reference invalid > 2s and no valid input clock available [selected reference invalid or (revertive mode and valid higher-priority input)] and valid input clock available phase-locked to selected reference > 2s notes: ? an input clock is valid when it has no ac tivity alarm and no phase lock alarm (see the valsr registers and the isr registers). ? all input clocks are continuous ly monitored for activity. ? only the selected reference is monitored for loss of lock. ? phase lock is declared internally when the dpll has maintai ned phase lock continuously for approximately 1 to 2 seconds. ? to simply the diagram, the phase-lock timeout period is always shown as 100s, which is the default value of the phlkto register. longer or shorter timeout periods can be specified as needed by writi ng the appropriate value to the phlkto register. ? when selected reference is invalid and the dpll is not in fr ee-run or holdover, the dpll is in a temporary holdover state.
________________________________________________________________________________________ ds 3104-se 28 7.7.1.3 locked state the t0 dpll state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states when the dpll has locked to the selected reference for at least 2 seconds (see section 7.7.6 ). in the locked state the output clocks track the phase and fr equency of the selected reference. if the mcr1 .lockpin bit is set, the lock pin is driven hi gh when the t0 dpll is in the locked state. while in the locked state, if the selected reference is so impaired that an activity alarm is raised (corresponding act bit set in the isr register), then the selected reference is invalidated (icn bit goes low in valsr registers), and the state machine immediately transitions to either the prelocked 2 state (if another valid input clock is available) or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid). if loss-of-lock (see section 7.7.6 ) is declared while in the locked state then the state machine transitions to the loss- of-lock state. 7.7.1.4 loss-of-lock state when the loss-of-lock detectors (see section 7.7.6 ) indicate loss of phase lock, the state machine immediately transitions from the locked state to the loss-of-lock stat e. in the loss-of-lock state the dpll tries for 100 seconds (default value of phlkto register) to regain phase lock. if phase lock is regained during that period for more than 2 seconds, the state machine transi tions back to the locked state. if, during the phase-lock tim eout period specified by phlkto , the selected reference is so impaired that an activity alarm is raised (corresponding act bit set in the isr registers), then the selected reference is invalidated (icn bit goes low in valsr registers), and after being invalid for 2 seconds the state machine transitions to either the prelocked 2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid). if phase lock cannot be regained by t he end of the phase-lock timeout period then a phase lock alarm is raised (corresponding lock bit set in the isr registers), the selected reference is invalidated (icn bit goes low in valsr registers), and the state machine transiti ons to either the prelocked 2 state (if another valid input clock is available) or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid). 7.7.1.5 prelocked 2 state the prelocked and prelocked 2 states are similar. the pr elocked 2 state provides a 100-second period (default value of phlkto register) for the dpll to lock to the new selected reference. if phase lock (see section 7.7.6 ) is achieved for more than 2 seconds during this period then the state machine transitions to locked mode. if the dpll fails to lock to the new selected reference within the phase-lock timeout period specified by phlkto then a phase lock alarm is raised (corresponding lock bit set in the isr registers), invalidating the input (icn bit goes low in valsr registers). if another input clock is valid then the state machine re-enter s the prelocked 2 state and tries to lock to the alternate input clock. if no other input clocks are valid for 2 seconds, the state machine transitions to the holdover state. in revertive mode (revert = 1 in mcr3 ), if a higher priority input clock becomes valid during the phase-lock timeout period then the state machine re- enters the prelocked 2 state and tries to lock to the higher priority input. if a phase-lock timeout period longer than 100 seconds is required for locking, then the phlkto register must be configured accordingly. 7.7.1.6 holdover state the device reaches the holdover stat e when it declares its selected reference invalid for 2 seconds and has no other valid input clocks available. during holdover the t0 dpll is not phase locked to any input clock but instead generates its output frequency from stored frequency informat ion acquired while it was in the locked state. when at least one input clock has been declared valid the state ma chine immediately transitions from holdover to the prelocked 2 state and tries to lock to the highest priority valid clock.
________________________________________________________________________________________ ds 3104-se 29 7.7.1.6.1 automatic holdover for automatic holdover (frunho = 0 in mcr3 ), the device can be further conf igured for instantaneous mode or averaged mode. in instantaneous mode (avg = 0 in hocr3 ), the holdover frequency is set to the dpll?s current frequency 50 to 100 ms before entry into holdover (i.e., the value of the freq field in the freq1 , freq2 and freq3 registers when mcr11 :t4t0 = 0). the freq field is the dpll?s integral path and therefore is an average frequency with a rate of change inversely proportional to the dpll bandwidth. the dpll?s proportional path is not used in order to minimize the effect of recent phase disturbances on the holdover frequency. in averaged mode (avg = 1 in hocr3 and frunho = 1 in mcr3 ), the holdover frequency is set to an internally averaged value. during locked operation the frequency indica ted in the freq field is internally averaged over a one-second period. the t0 dpll indicates that it has acquired a valid holdover value by setting the hordy status bit in valsr2 (real-time status) and msr4 (latched status). if the t0 dpll must enter holdover before the one-second average is available, an instantaneous value 50ms to 100ms old from the integral path is used instead. 7.7.1.6.2 free-run holdover for free-run holdover (frunho = 1 in mcr3 ), the output frequency accuracy is generated with the accuracy of the external oscillator fr equency. the actual frequen cy is the frequency of the external oscillator plus the value of the mclk offset specified in the mclkfreq field in registers mclk1 and mclk2 (see section 7.3 ). when mcr3.frunho is set the hocr3 :avg bit is ignored. 7.7.1.7 mini-holdover when the selected reference fails, t he fast activity monitor (section 7.5.3 ) isolates the t0 dpll from the reference within one or two clock cycles to avoid adverse effects on the dpll frequency. when this fast isolation occurs, the dpll enters a temporary mini-holdover mode, with a fr equency equal to an instantaneous value 50ms to 100 ms old from the integral path of the loop filter. mini-holdove r lasts until the selected reference becomes active or the state machine enters the holdover state. if the free-run holdover mode is set (frunho = 1 in mcr3 ), the mini- holdover frequency accuracy is exactly the same as the external oscillator accuracy plus the offset set by the mclkfreq field in registers mclk1 and mclk2 (see section 7.3 ). 7.7.2 t4 dpll state machine the t4 dpll state machine is similar to the t0 dpll, as shown in figure 7-3 . the t4 dpll states are similar to the equivalent states of the t0 dpll but the onl y state indicator is the t4lock bit in the opstate register. note that the t4 dpll only operates in revertive switchi ng mode. the full-holdover and mini-holdover modes are instantaneous (see the first paragraph of section 7.7.1.6.1 ).
________________________________________________________________________________________ ds 3104-se 30 figure 7-3. t4 dpll state transition diagram free-run pre-locked reset selected reference active selected reference inactive > 2 sec locked phase-locked to selected reference > 2 sec loss-of-lock holdover loss-of-lock on selected reference phase-lock regained on selected reference > 2 sec pre-locked 2 selected reference inactive > 2 sec selected reference switch selected reference inactive > 2 sec selected reference active selected reference inactive > 2sec selected reference switch selected reference phase-locked > 2sec
________________________________________________________________________________________ ds 3104-se 31 7.7.3 bandwidth the bandwidth of the t4 dpll is configured in the t4bw register to be 18hz to 70hz. the bandwidth of the t0 dpll is configured in the t0abw and t0lbw registers for various values from 0.1hz to 400hz. the autobw bit in the mcr9 register controls automatic bandwid th selection. when autobw = 1, the t0 dpll uses the t0abw bandwidth during acquisition ( not phase locked) and the t0lbw bandwidth when phase locked. when autobw = 0 the t0 dpll uses the t0lbw bandwidth all the time, both during acquisition and when phase locked. when limint = 1 in the mcr9 register, the dpll?s integral path is lim ited (i.e., frozen) when the dpll reaches minimum or maximum frequency. setting limint = 1 minimizes overshoot when the dpll is pulling in. 7.7.4 damping factor the damping factor for the t0 dpll is configured in the damp field of the t0cr2 register, while the damping factor of the t4 dpll is conf igured in the damp field of the t4cr2 register. the reset default damping factors for both dplls are chosen to give a maximum jitter/wander gain peak of approximately 0.1db. available settings are a function of dpll bandwidth (configured in the t4bw , t0abw , and t0lbw registers). see table 7-4 . table 7-4. damping factors and peak jitter/wander gain bandwidth (hz) damp[2:0] value damping factor gain peak (db) 0.1 to 4 1, 2, 3, 4, 5 5 0.1 1 2.5 0.2 8 2, 3, 4, 5 5 0.1 1 1.2 0.4 2 2.5 0.2 18 3, 4, 5 5 0.1 1 1.2 0.4 2 2.5 0.2 3 5 0.1 35 4, 5 10 0.06 1 1.2 0.4 2 2.5 0.2 3 5 0.1 4 10 0.06 70 to 400 5 20 0.03 7.7.5 phase detectors phase detectors are used to compare a pll?s feedback cloc k with its input clock. several phase detectors are available in the t0 and t4 dplls: ? phase/frequency detector (pfd) ? early/late phase detector (pd2) for fine resolution ? multicycle phase detector (mcpd) for large i nput jitter tolerance and/or faster lock times these detectors can be used in combination to give fine ph ase resolution combined with large jitter tolerance. as with the rest of the dpll logic, the phase detectors operate at input frequencies up to 77.76mhz. the multicycle phase detector detects and remembers phase differences of many cycles (up to 8191ui). when locking to 8khz or lower, the normal phase/frequency detectors are always used.
________________________________________________________________________________________ ds 3104-se 32 the t0 dpll phase detectors can be configured for normal phase/frequency locking ( 360 capture) or nearest- edge phase locking ( 180 capture). with nearest-edge detection the phase detectors are immune to occasional missing clock cycles. the dpll automatically switches to nearest-edge locking when the multicycle phase detector is disabled and the other phase detectors determine that phase lock has been achieved. setting d180 = 1 in the test1 register disables nearest-edge locking and forces the t0 dpll to use phase/frequency locking. the t4 dpll always has nearest edge locking enabled. the early/late phase detector, also known as phase detecto r 2, is enabled and configured in the pd2* fields of registers t0cr2 and t0cr3 for the t0 dpll and registers t4cr2 and t4cr3 for the t4 dpll. the reset default settings of these registers are appropri ate for all operating modes. adjustment s only affect small signal overshoot and bandwidth. the multicycle phase detector is enabled by setting mcpden = 1 in the phlim2 register. the range of the mcpd?from 1ui up to 8191ui?is configured in the coarselim field of phlim2 . the mcpd tracks phase position over many clock cycles, giving high jitter tolerance. thus the use of the mcpd is an alternative to the use of lock8k mode for jitter tolerance. when a dpll is direct locking to 8khz, 4khz, or 2khz or in lock8k mode, the multicycle phase detector is automatically disabled. when usemcpd = 1 in phlim2 , the mcpd is used in the dpll loop, givi ng faster pull-in but more overshoot. in this mode the loop has similar behavior to lock8k mode. in both cases large phase differences contribute to the dynamics of the loop. when enabled by mcpden = 1, the mcpd tracks the phase position whether or not it is used in the dpll loop. when the input clock is divided before being sent to the phase detector, the divider output clock edge gets aligned to the feedback clock edge before the dpll starts to lock to a new input clock signal or after the input clock signal has a temporary signal loss. this helps ensure locking to the nearest input clock edge which reduces output transients and decreases lock times. 7.7.6 loss of phase lock detection loss of phase lock can be triggered by any of the following in both the t0 and t4 dplls: ? the fine phase lock detector (measures phase between input an d feedback clocks) ? the coarse phase lock detector (measures whole cycle slips) ? hard frequency limit detector ? inactivity detector the fine phase lock detector is enabled by setting flen = 1 in the phlim1 register. the fine phase limit is configured in the finelim field of phlim1 . the coarse phase lock detector is enabled by setting clen = 1 in the phlim2 register. the coarse phase limit is configured in the coarselim field of phlim2 . this coarse phase lock detector is part of the multicycle phase detector (mcpd) described in section 7.7.5 . the coarselim field sets both the mcpd range and the coarse phase limit, since the two are equivalent. if loss of phase lo ck should not be declared for multiple-ui input jitter then the fine phase lock detector should be disabled and the coarse phase lock detector should be used instead. the hard frequency limit detector is enabled by setting fllol = 1 in the dlimit3 register. the hard limit for the t0 dpll is configured in registers dlimit1 and dlimit2 . the t4 dpll hard limit is fixed at 80ppm. when the dpll frequency reaches the hard limit, loss-of-lock is declared. the dlimit3 register also has the softlim field to specify a soft frequency limit. exceeding the soft frequency lim it does not cause loss-of-lock to be declared. when the t0 dpll frequency reaches the soft limit the t0soft status bit is set in the opstate register. when the t4 dpll frequency reaches the soft limit the t4soft status bit is set in opstate . both the soft and hard alarm limits have hysteresis as required by gr-1244. the inactivity detector is enabled by setting nalol = 1 in the phlim1 register. when this detector is enabled the dpll declares loss-of-lock after one or two missing clock cycles on the select ed reference. see section 7.5.3 .
________________________________________________________________________________________ ds 3104-se 33 when the t0 dpll declares loss of phase lock, the state ma chine immediately transitions to the loss-of-lock state, which sets the state bit in the msr2 register and requests an interrupt if enabled. when the t4 dpll declares loss of phase lock, the t4lock bit is cleared in the opstate register, which sets the t4lock bit in the msr3 register and requests an interrupt if enabled. 7.7.7 phase build-out 7.7.7.1 automatic phase build-out in response to reference switching when mcr10 :pboen = 0, phase build-out is not performed duri ng reference switching. the t0 dpll always locks to the selected reference at zero degrees of phase. with pbo disabled, transitions from a failed reference to the next highest priority reference and transitions from holdover or free-run to locked mode cause phase transients on output clocks as the t0 dpll jumps from its previous phase to the phase of the new selected reference. when mcr10 :pboen = 1, phase build-out is performed during refe rence switching (or exiting from holdover). with pbo enabled, if the selected reference fails and another valid reference is available then the device enters a temporary holdover state in which the phase difference between the new reference and the output is measured and fed into the dpll loop to absorb the input phase diffe rence. similarly, during transitions from full-holdover, mini-holdover or free-run to locked mode, the phase difference between the new reference and the output is measured and fed into the dpll loop to absorb the input phase difference. after a pbo event, regardless of the input phase difference, the output phase tr ansient is less than or equal to 5ns. any time that pbo is enabled it can also be frozen at the current phase offset by setting mcr10 :pbofrz = 1. when pbo is frozen the t0 dpll ignores subsequent phase build-out events and maintains the current phase offset between inputs and outputs. disabling pbo while the t0 dpll is not in the free-run or holdover states (locking or locked) will cause a phase change on the output clocks while the dpll switches to tr acking the selected reference with 0 degrees of phase error. the rate of phase change on the output cloc ks depends on the dpll bandwidth. enabling pbo (which includes un-freezing) while locking or locked also causes a pbo event. 7.7.7.2 pbo phase offset adjustment an uncertainty of up to 5ns is introduced each time a pha se build-out event occurs. this uncertainty results in a phase hit on the output. over a large number of phas e build-out events the mean error should be zero. the pboff register specifies a small fixed offset for each phase bu ild-out event to skew the average error toward zero and eliminate accumulation of phase shifts in one direction. 7.7.8 input to output (manual) phase adjustment when phase build-out is disabled (pboen = 0 in mcr10 ), the offset registers can be used to adjust the phase of the t0 dpll output clocks with respect to the sele cted reference when locked. output phase offset can be adjusted over a 200ns range in 6ps increments. this phase adjustm ent occurs in the feedback clock so that the output clocks are adjusted to compensate. the rate of ch ange is therefore a function of dpll bandwidth. simply writing to the offset registers with phase build-out disabled causes a change in the input to output phase, which can be considered to be a delay adjustment. changing the offset adjustment while in free-run or holdover state will not cause an output phase offset until it exit s the state and enters one of the locking states. 7.7.9 phase recalibration when a phase buildout occurs, either automatic or m anual, the feedback frequency sy nthesizer does not get an internal alignment signal to keep it aligned with the output dividers, and therefore the phase difference between input and output may become incorrect. setting the fscr3 :recal bit periodically causes a recalibration process to be executed which corrects any phase error that may have occurred.
________________________________________________________________________________________ ds 3104-se 34 during the recalibration process the device puts the dpll into mini-holdover, internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the offset registers, and then switches the dpll out of mini-holdover. if the offset registers are written during the recalibration process, the process will ramp the phase offset to the new offset value. 7.7.10 frequency and p hase measurement when the t4 dpll is not needed to generate an output fr equency locked to an input clock it can measure precise frequency by locking onto any input. it can also measur e phase between the t0 selected reference and any input by setting the t0cr1 .t4mt0 bit. the t4 apll can still be used to clean up jitter on a synthesized clock from the t0 dpll. when the t0cr1 .t4mt0 bit is set the t4 dpll goes to the free-run state. accurate measurement of frequency and phase can be ac complished using the dplls. the t0 dpll is always monitoring its selected reference, but the t4 dpll can be configured as a high-resolution phase monitor. the refclk signal accuracy after being adjus ted with mclkfreq is used for the frequency reference. software can then connect the t4 dpll to various input clocks on a ro tating basis to measure phase between the t0 dpll input and another input. see the t4force field of mcr4 . dpll frequency measurements can be read from the freq field spanning registers freq1 , freq2 and freq3 . this field indicates the frequency of the selected refere nce for either the t0 dpll or the t4 dpll, depending on the setting of the t4t0 bit in mcr11 . this frequency measurement has a resolution of 0.0003068ppm over a 80ppm range. the value read from the freq field is the dpll?s integral path value, which is an averaged measurement with an averaging time inversely proportional to dpll bandwidth. dpll phase measurem ents can be read from the phase field spanning registers phase1 and phase2 . this field indicates the phase difference seen by the phase det ector for either the t0 dpll or the t4 dpll, depending on the setting of the t4t0 bit in mcr11 . this phase measurement has a reso lution of approximately 0.703 degrees and is internally averaged with a -3db attenuation point of approximately 100hz. thus for low dpll bandwidths the phase field gives input phase wander in the frequency band from the dpll corner frequenc y up to 100hz. this information could be used by software to compute a crude mtie measurement. for the t0 dpll the phase field always indicates t he phase difference between the selected reference and the internal feedback clock. the t4 dpll, however, can be configured to measure the phase difference between two input clocks. when t0cr1 :t4mt0 = 1, the t4 dpll locking capability is disabled and the t4 phase detector is configured to compare the t0 dpll selected reference wi th the t4 dpll selected reference. any input clock can then be forced to be the t4 dpll selected reference using the t4force field of mcr4 . this feature can be used, for example, to measure the phase difference betw een the t0 dpll?s selected reference and its next highest priority reference. software could compute mtie and tdev with respect to the t0 dpll selected reference for any or all of the other input clocks. when comparing the phase of the t0 and t4 selected references by setting t0cr1 :t4mt0 = 1, several details must be kept in mind. in this mode, the t4 path receives a copy of the t0 selected refe rence, either directly or through a divider to 8khz. if the t4 selected reference is divided down to 8khz using lock8k or divn modes (see section 7.4.2 ), then the copy of the t0 selected reference is also divided down to 8khz. if the t4 selected reference is configured for direct-lock mode, then the copy of the t0 selected reference is not divided down and must be the same frequency as the t4 selected reference. see table 7-5 for more details. (while t0cr1 :t4mt0 = 1, the t0 path continues to lock to the t0 selected reference in the manner specified in the corresponding icr register.)
________________________________________________________________________________________ ds 3104-se 35 table 7-5. t0 dpll adaptation for th e t4 dpll phase measurement mode locking mode for t4 selected reference locking mode for t0 selected reference locking mode for copy of t0 selected ref frequency of the t4 selected ref for t4mt0 phase measurement frequency of the t0 selected ref for t4mt0 phase measurement lock8k or divn(8k) direct lock8k 8khz 8khz lock8k or divn(8k) lock8k lock8k 8khz 8khz lock8k or divn(8k) divn (8k) divn 8khz 8khz lock8k or divn(8k) divn (not 8k) direct 8khz 8khz divn (not 8k) any direct same as the t4 forced ref input frequency same as the t0 selected ref input frequency (1) direct any direct same as the t4 forced ref input frequency same as the t0 selected ref input frequency (1) note 1: in this case the t0 select reference must be the same frequency as the t4 selected reference. note 2: if the t4 selected reference frequency is 8khz and the t0 select ed reference is a different frequency, the two references can be compared by configuring the t4 selected reference for 8khz and lock 8k mode. this forces the copy of the t0 selected reference t o be divided down to 8khz using either lock8k or divn mode. note 3: divn(8k) means that the freq field is set to 8khz, divn(not 8k) means the freq field is not set to 8khz. 7.7.11 input jitter tolerance the device is compliant with the jitter tolera nce requirements of the standards listed in table 1-1 . when using the 360 / 180 pfd, jitter can be tolerated up to the point of eye closure. either lock8k mode (see section 7.4.2.2 ) or the multicycle phase detector (see section 7.7.5 ) should be used for high jitter tolerance. 7.7.12 jitter and wander transfer the transfer of jitter and wander from the selected re ference to the output clocks has a programmable transfer function that is determined by the dpll bandwidth. (see section 7.7.3 .) in the t0 dpll, the 3db corner frequency of the jitter transfer function can be set to any of 13 posi tions from 0.1hz to 400hz. in the t4 dpll the 3db corner frequency of the jitter transfer function can be set to various values from 18hz to 70hz. during locked mode, the transfer of wander from the loca l oscillator clock (connected to the refclk pin) to the output clocks is not significant as long as the dpll ban dwidth is set high enough to allow the dpll to quickly compensate for oscillator fr equency changes. during free-run and hol dover modes, local osc illator wander has a much more significant effect. see section 7.3 .
________________________________________________________________________________________ ds 3104-se 36 7.7.13 output jitter and wander several factors contribute to jitter and wander on the output clocks, including: ? jitter and wander amplitude on the selected re ference (while in the locked state) ? the jitter/wander transfer c haracteristic of the device (while in the locked state) ? the jitter and wander on the local oscillator clock signal (especially wander while in the holdover state) the dpll in the device has progr ammable bandwidth (see section 7.7.3 ). with respect to jitter and wander, the dpll behaves as a low-pass f ilter with a programmable pole. the bandwidth of the dpll is normally set low enough to strongly attenuate jitter. the wander and ji tter attenuation depends on the dpll bandwidth chosen. over time frequency changes in the local oscillator can cause a phase difference between the selected reference and the output clocks. this is especially true at lower frequency dpll bandwidths because the dpll?s rate of change may be slower than the oscillator?s rate of change. oscillators with better stability will minimize this effect. in the most demanding applications an ocxo may be required rather than a tcxo.
________________________________________________________________________________________ ds 3104-se 37 7.8 output clock configuration a total of 18 output clock pins, oc1 to oc5, oc1b to oc5b, oc4pos/neg to oc7pos/neg and fsync and mfsync are available on the device. ou tput clocks oc1 to oc7 are individually configurable for a variety of frequencies derived from either the t0 dpll or the t4 dpll. oc1b to oc5b are powered from a dedicated io power pin which can be set to any voltage from 2.2v to 3.3v. output clocks fsync and mfsync serve as 8khz frame sync and 2khz multiframe sync outputs, respectively. table 7-6 provides more detail on the capabilities of the output clock pins. table 7-6. output clock capabilities output clock signal format frequencies supported oc1 oc2 oc3 oc4 oc5 cmos/ttl 3.3v powered oc1b oc2b oc3b oc4b oc5b cmos/ttl 2.5v or 3.3v powered oc4 oc5 oc6 oc7 lvds/lvpecl frequency selection per section 7.8.2.3 and table 7-7 to table 7-13 . fsync 8khz frame sync with prog rammable pulse width and polarity. mfsync cmos/ttl 2khz multiframe sync with programmable pulse width and polarity. 7.8.1 signal format configuration output clocks oc4, oc5, oc6, and oc7 are lv ds-compatible, lvpecl le vel-compatible outputs. the type of output can be selected or the output can be disabl ed using the ocnsf config uration bits in the mcr8 register. the lvpecl level-compatible mode generates a differential signal that is large enough for most lvpecl receivers. some lvpecl receivers have a limited common mode si gnal range which can be ac commodated for by using an ac coupled signal. the lvds electrical specifications are listed in table 10-5 , and the recommended lvds termination is shown in figure 10-1 . the lvpecl level-compatible electr ical specifications are listed in table 10-6 , and the recommended lvpecl receiver termination is shown in figure 10-3 . these differential outputs can be easily interfaced to lvds, lvpecl and cml inputs on neig hboring ics using a few exte rnal passive components. see maxim app note hfan-1.0 for details. the other output clocks are cmos/ttl signal format. 7.8.2 frequency configuration the frequency of output clocks oc1 to oc7 is a function of the settings used to configure the components of the t0 and t4 pll paths. these components are shown in the detailed block diagram of figure 7-1 . the DS3104-se uses digital frequency sy nthesis (dfs) to generate various cl ocks. in dfs a high-speed master clock (204.8mhz) is divided down to the desired output frequency by adding a number to an accumulator. the dfs output is a coding of the clock output ph ase which is used by a special circui t to determine where to put the edges of the output clock between the clock e dges of the master clock. the edges of the output clock, however, are not ideally located in time resulting in jitter wi th an amplitude typically less than 1ns pk-pk.
________________________________________________________________________________________ ds 3104-se 38 7.8.2.1 t0 and t4 dpll details see figure 7-1 . the t0 and t4 forward dfs blocks use the 204.8mhz master clock and dfs technology to synthesize internal clocks from which the output and f eedback clocks are derived. the t4 dpll only has a single dfs output clock signal for both the output clocks and the feedback clock, wh ereas there are two dfs output clock signals in the t0 dpll, one for the outpu t clocks and one for the feedback clock. in the t0 dpll the feedback clock sig nal output handles phase build-out or any phase offset configured in the offset registers. thus the t0 dpll ou tput clock signals and the feedback clock signal are frequency locked but may have a phase offset. the t0 and t4 feedback dfs bl ocks are always connected to the t0 forward dfs and the t4 forward dfs, respectively. the feedback dfs blocks synthesize the appropriate locking frequencies for use by the phase-frequency detectors (pfds). see section 7.4.2 . 7.8.2.2 output dfs and apll details see figure 7-1 . the output clock frequencies are determined by two 2khz/8khz dfs blocks, two dig12 dfs blocks, and three apll dfs blocks. four of the dfs blocks can be connected to either the t0 dpll or the t4 dpll, three are always connected to the t0 dpll. the t0 apll, the t0 apll2 and t he t4 apll (and their output dividers) get their frequency references from three asso ciated apll dfs blocks. all of the output dfs blocks are connected to the t0 dpll when mcr4 :lkt4t0 = 1. the 2k8k dfs and fsync dfs blocks generate both 2khz and 8khz signals which have about 1ns pk-pk jitter. the fsync (8khz) and mfsync(2 khz) signals come from t he fsync dfs block, which is always connected to the t0 dpll when not in independent mode ( fscr2 :indep = 1). the 2khz and 8khz signals available on output clocks oc1 to oc7 come from the 2k8k dfs, which c an be connected to either the t0 dpll or the t4 dpll depending on fscr1 :2k8ksrc and mcr4 :lkt4t0. the dig1 dfs can generate an nxds1 or nxe1 signal with about 1ns pk-pk jitter. the dig2 dfs can generate an nxds1, nxe1, 6.312mhz, 10mhz, or nx19. 44mhz clock with approximately 1ns pk-pk jitter. each dig12 dfs can be connected to either the t0 dpll or the t4 dpll using mcr7 :dig1src or mcr7 :dig2src and mcr4 :lkt4t0. the frequency of the dig1 cloc k is configured by the dig1ss bit in mcr6 and the dig1f[1:0] field in mcr7 . the frequency of the dig2 clock is conf igured by the dig2af and dig2ss bits in mcr6 and the dig2f[1:0] field in mcr7 . dig1 and dig2 can be independently config ured for any of the frequencies shown in table 7-7 and table 7-8 , respectively. the apll dfs blocks and their associated output ap lls and output dividers can generate many different frequencies. the t0 apll dfs and the t0 apll2 dfs are always connected to the t0 dpll. the t4 apll dfs can be connected to either the t0 dpll or the t4 dpll depending on t0cr1 :t4apt0 and mcr4 :lkt4t0. the t0 apll frequencies that can be generated are listed in table 7-10 . the t0 apll2 frequency is always 312.500mhz. the t4 apll frequencies that can be generated are listed in table 7-12 . the output frequencies that can be generated from the apll circuits are listed in table 7-9 . the t4 apll is disabled and powered down when t4cr1 :t4freq = 0000 and t0cr1 :t4apt0 = 0. in this mode all outputs connected to the t4 apll are driven low. together the t0 apll, t0 apll2 and t4 apll can simu ltaneously generate sonet/sdh clock rates, gigabit ethernet clock rates (e.g., 125mhz) and 10g ethernet cl ock rates (e.g., 156.25mhz), all locked to the same selected reference. this capabilit y supports mixed sonet/sdh and synchronous ether net line cards.
________________________________________________________________________________________ ds 3104-se 39 7.8.2.3 oc1 to oc 7 configuration the following is a step-by-step procedure for configuri ng the frequencies of output clocks oc1 through oc7: 1) determine whether the t4 apll must be ind ependent of the t0 dpll or not. if the t4 apll must be independent, set t4apt0 = 0 in register t0cr1 . if the t4 apll must be locked to the t0 dpll then set t4apt0 = 1. 2) use table 7-9 to select a set of output frequencies for each apll, t0 and t4. each apll can only generate one set of output frequencies. (in sonet/sdh equipment the t0 apll is typically configured for a frequency of 311.04mhz to get 19.44mhz and/or 38.88mhz output clocks to distribute to system line cards.) 3) determine from table 7-9 the t0 and t4 apll frequencies required for the frequency sets chosen in step 2. 4) configure the t0freq field in register t0cr1 as shown in table 7-10 for the t0 apll frequency determined in step 3. configure the t4freq field in register t4cr1 as shown in table 7-12 for the t4 apll frequency determined in step 3. if the t4 apll is locked to the t0 dpll, the t4apt0 and t0ft4 fields in t0cr1 must also be configured as shown in table 7-12 . 5) using table 7-9 and table 7-13 , configure the frequencies of output clocks oc1 through oc7 in the ofreqn fields of registers ocr1 through ocr4 and the aofn bit in the ocr5 register. table 7-14 lists all standard frequencies for the output clocks and specifies how to configure the t0 apll and/or the t4 apll to obtain each frequency. table 7-14 also indicates the expected jitter amplitude for each frequency. table 7-7. digital1 frequencies dig1f[1:0] setting in mcr7 dig1ss setting in mcr6 frequency (mhz) jitter (pk-pk ns, typ) 00 0 2.048 < 1 01 0 4.096 < 1 10 0 8.192 < 1 11 0 16.384 < 1 00 1 1.544 < 1 01 1 3.088 < 1 10 1 6.176 < 1 11 1 12.352 < 1 table 7-8. digital2 frequencies dig2af setting in mcr6 dig2f[1:0] setting in mcr7 dig2ss setting in mcr6 frequency (mhz) jitter (pk-pk ns, typ) 1 00 0 6.312 < 1 1 10 0 10.000 <1 1 00 1 19.440 < 1 1 01 1 38.880 < 1 0 00 0 2.048 < 1 0 01 0 4.096 < 1 0 10 0 8.192 < 1 0 11 0 16.384 < 1 0 00 1 1.544 < 1 0 01 1 3.088 < 1 0 10 1 6.176 < 1 0 11 1 12.352 < 1
________________________________________________________________________________________ ds 3104-se 40 table 7-9. apll frequenc y to output frequencies (t0 apll and t4 apll) apll frequency apll / 2 apll / 4 apll / 5 apll / 6 apll / 8 apll / 10 apll / 12 apll / 16 apll / 20 apll / 48 apll / 64 312.500 156.250 ? 62.500 ? ? 31.250 ? ? ? ? ? 311.040 155.520 77.760 62.208 51.840 38.880 31.104 25.920 19.440 15.552 6.480 4.860 274.944 137.472 68.376 ? 45.824 34.368 ? 22.912 17.184 ? 5.728 4.296 250.000 125.000 62.500 50.000 ? 31.250 25.000 ? ? 12.500 ? ? 178.944 89.472 44.736 ? 29.824 22.368 ? 14.91 2 11.184 ? 3.728 2.796 160.000 80.000 40.000 32. 00 ? 20.000 16.000 ? 10.000 8.000 ? 2.500 148.224 74.112 37.056 ? 24.704 18.528 ? 12.352 9.264 ? 3.088 2.316 131.072 65.536 32.768 ? ? 16.384 ? ? 8.192 ? ? 2.048 122.880 61.440 30.720 24.576 20.48 15.360 12.288 10.240 7.680 6.144 2.560 1.920 104.000 52.000 26.000 20.800 ? 13.000 10.400 ? 6.500 5.200 ? ? 100.992 50.496 25.248 ? 16.832 12.624 ? 8.416 6.312 ? 2.104 1.578 98.816 49.408 24.704 ? ? 12.352 ? ? 6.176 ? ? 1.544 98.304 49.152 24.576 ? 16.384 12.288 ? 8.192 6.144 ? 2.048 1.536 note: all frequencies in mhz. common telecom, datacom and synchronization frequencies are in bold type. table 7-10. t0 apll fr equency configuration t0 apll frequency (mhz) t0 apll dfs frequency (mhz) t0 apll frequency mode t0freq[2:0] setting in t0cr1 output jitter (pk-pk, ns, typ) 311.04 77.76 77.76mhz 000 < 0.5 311.04 77.76 77.76mhz 001 < 0.5 98.304 24.576 12 x e1 010 < 0.5 131.072 32.768 16 x e1 011 < 0.5 148.224 37.056 24 x ds1 100 < 0.5 98.816 24.704 16 x ds1 101 < 0.5 100.992 25.248 4 x 6312khz 110 < 0.5 250.000 62.5 gbe 16 111 < 0.5 table 7-11. t0 apll2 fr equency configuration t0 apll2 frequency (mhz) t0 apll2 dfs frequency(mhz) output jitter (pk-pk, ns, typ) 312.500 62.500 <0.5
________________________________________________________________________________________ ds 3104-se 41 table 7-12. t4 apll fr equency configuration t4 apll frequency (mhz) t4 apll dfs frequency (mhz) t4 apll frequency mode t4apt0 setting in t0cr1 t4freq[3:0] setting in t4cr1 t0ft4[2:0] setting in t0cr1 output jitter (pk-pk, ns, typ) disabled 77.76 squelched 0 0000 xxx < 0.5 311.04 77.76 77.76mhz 0 0001 xxx < 0.5 98.304 24.576 12 x e1 0 0010 xxx < 0.5 131.072 32.768 16 x e1 0 0011 xxx < 0.5 148.224 37.056 24 x ds1 0 0100 xxx < 0.5 98.816 24.704 16 x ds1 0 0101 xxx < 0.5 274.944 68.736 2 x e3 0 0110 xxx < 0.5 178.944 44.736 ds3 0 0111 xxx < 0.5 100.992 25.248 4 x 6312khz 0 1000 xxx < 0.5 250.000 62.500 gbe 16 0 1001 xxx < 0.5 122.88 30.720 3 x 10.24 0 1010 xxx < 0.5 160.000 40.000 4 x 10 0 1011 xxx < 0.5 104.000 26.000 2 x 13 0 1100 xxx < 0.5 98.304 24.576 t0 12 x e1 1 xxxx 000 < 0.5 250.000 62.500 t0 gbe 16 1 xxxx 001 < 0.5 131.072 32.768 t0 16 x e1 1 xxxx 010 < 0.5 148.224 37.056 t0 24 x ds1 1 xxxx 100 < 0.5 98.816 24.704 t0 16 x ds1 1 xxxx 110 < 0.5 100.992 25.248 t0 4 x 6312khz 1 xxxx 111 < 0.5 table 7-13. oc1?oc7 out put frequency selection frequency aof bit ofreq (1) oc1 oc2 oc3 oc4 oc5 oc6 oc7 0 0000 disabled disabled disabled disabled disabled disabled disabled 0 0001 2khz 2khz 2khz 2khz 2khz 2khz 2khz 0 0010 8khz 8khz 8khz 8khz 8khz 8khz 8khz 0 0011 digital2 digital2 digital2 dig ital2 digital2 t0 / 2 digital 2 0 0100 digital1 digital1 digital1 dig ital1 digital1 digital1 t0 / 2 0 0101 t0 / 48 t0 / 48 t0 / 48 t0 / 48 t0 / 48 t0 / 1 t0 / 48 0 0110 t0 / 16 t0 / 16 t0 / 16 t0 / 16 t0 / 16 t0 / 16 t0 / 16 0 0111 t0 / 12 t0 / 12 t0 / 12 t0 / 12 t0 / 12 t0 / 12 t0 / 12 0 1000 t0 / 8 t0 / 8 t0 / 8 t0 / 8 t0 / 8 t0 / 8 t0 / 8 0 1001 t0 / 6 t0 / 6 t0 / 6 t0 / 6 t0 / 6 t0 / 6 t0 / 6 0 1010 t0 / 4 t0 / 4 t0 / 4 t0 / 4 t0 / 4 t0 / 4 t0 / 4 0 1011 t4 / 64 t4 / 64 t4 / 64 t4 / 2 t4 / 2 t4 / 64 t4 / 64 0 1100 t4 / 48 t4 / 48 t4 / 48 t4 / 48 t4 / 48 t4 / 48 t4 / 48 0 1101 t4 / 16 t4 / 16 t4 / 16 t4 / 16 t4 / 16 t4 / 16 t4 / 16 0 1110 t4 / 8 t4 / 8 t4 / 8 t4 / 8 t4 / 8 t4 / 8 t4 / 8 0 1111 t4 / 4 t4 / 4 t4 / 4 t4 / 4 t4 / 4 t4 / 4 t4 / 4 1 0000 disabled disabled disabled disabled disabled disabled disabled 1 0001 t0 / 64 t0 / 64 t0 / 64 t0 / 2 t0 / 2 t4 / 5 t4 / 5 1 0010 t4 / 20 t4 / 20 t4 / 20 t0 / 1 t0 / 1 t4 / 2 t4 / 2 1 0011 t4 / 12 t4 / 12 t4 / 12 t4 / 10 t4 / 10 t4 / 1 t4 / 1 1 0100 t4 / 10 t4 / 10 t4 / 10 t02 / 10 t02 / 10 t02 / 5 t02 / 5 1 0101 t02 / 10 t4 / 5 t4 / 5 t02 / 2 t02 / 2 t02 / 2 t02 / 2 1 0110 t02 / 5 t4 / 2 t4 / 2 t02 / 1 t02 / 1 t02 / 1 t02 / 1 1 0111 t4selref t4selref t4selref t4selref t4selref t4selref t4selref note 1: the value of the ofreqn field (in the ocr1 through ocr4 registers) corresponding to output clock ocn. note 2: t0 = t0 apll. t02 = t0 apll2. t4 = t4 apll.
________________________________________________________________________________________ ds 3104-se 42 table 7-14. standard frequenc ies for programmable outputs t0 apll t4 apll jitter (typ) frequency (mhz) t0freq t4ft0 t4freq ofreqn rms (ps) pk-pk (ns) 2khz 2khz 100 1.00 8khz 8khz 100 1.00 1.536 not oc4, oc5 from t4 apll not oc4 to oc7 from t0 apll 12 x e1 12 x e1 12 x e1 apll/64 50 0.50 1.544 not oc6 from dig2 dig1,dig2 100 1.00 1.544 not oc4, oc5 from t4 apll not oc4 to oc7 from t0 apll 16 x ds1 16 x ds1 16 x ds1 apll/64 50 0.50 1.578 not oc4, oc5 from t4 apll not oc4 to oc7 from t0 apll 4 x 6.312 4 x 6.312 4 x 6.312 apll/64 50 0.50 2.048 not oc6 from dig2 dig1,dig2 100 1.00 2.048 not oc6 from t0 apll 12 x e1 12 x e1 12 x e1 apll/48 50 0.50 2.048 not oc4, oc5 from t4 apll not oc4 to oc7 from t0 apll 16 x e1 16 x e1 16 x e1 apll/64 50 0.50 2.104 not oc6 from t0 apll 4 x 6.3 12 4 x 6.312 4 x 6. 312 apll/48 50 0.50 2.316 not oc4, oc5 from t4 apll not oc4 to oc7 from t0 apll 24 x ds1 24 x ds1 24 x ds1 apll/64 50 0.50 2.500 not oc4, oc5 4 x 10 apll/64 50 0.50 2.560 3 x 10.24 apll/48 50 0.50 2.796 not oc4, oc5 ds3 apll/64 50 0.50 3.088 not oc6 from dig2 dig1,dig2 100 1.00 3.088 not oc6 from t0 apll 24 x ds 1 24 x ds1 24 x ds1 apll/48 50 0.50 3.728 ds3 apll/48 50 0.50 4.096 not oc6 from dig2 dig1,dig2 100 1.00 4.296 not oc4, oc5 2 x e3 apll/64 50 0.50 4.860 not oc4, oc5 from t4 apll not oc4 to oc7 from t0 apll 77.76 77.76 apll/64 50 0.50 5.200 oc1-oc3 only 2 x 13 apll/20 50 0.50 5.728 2 x e3 apll/48 50 0.50 6.144 oc1-oc3 only 3 x 10.24 apll/20 50 0.50 6.144 12 x e1 12 x e1 12 x e1 apll/16 50 0.50 6.176 not oc6 from dig2 dig1,dig2 100 1.00 6.176 16 x ds1 16 x ds1 16 x ds1 apll/16 50 0.50 6.312 not oc6 dig2 100 1.00 6.312 4 x 6.312 4 x 6.312 4 x 6.312 apll/16 50 0.50 6.480 not oc6 from t0 apll 77.76 77.76 apll/48 60 0.6 8.000 oc1-oc3 only 4 x 10 apll/20 50 0.50 8.192 not oc6 from dig2 dig1,dig2 100 1.00 8.192 12 x e1 apll/12 50 0.50 8.192 16 x e1 16 x e1 16 x e1 apll/16 50 0.50 8.416 4 x 6.312 apll/12 50 0.50 9.264 24 x ds1 24 x ds1 24 x ds1 apll/16 50 0.50 10.000 not oc6 dig2 100 1.00 10.000 4 x 10 apll/16 50 0.50 10.240 oc1-oc3 only 3 x 10.24 apll/12 50 0.50 10.400 not oc6, oc7 3 x 10.24 apll/10 50 0.50 11.184 ds3 apll/16 50 0.50 12.288 12 x e1 12 x e1 12 x e1 apll/8 50 0.50 12.288 not oc6, oc7 2 x 13 apll/10 50 0.50 12.352 24 x ds1 apll/12 50 0.50 12.352 16 x ds1 16 x ds 1 16 x ds1 apll/8 50 0.50 12.352 not oc6 from dig2 dig1,dig2 100 1.00 12.500 oc1-oc3 only gbe 16 gbe 16 apll/20 50 0.50 12.624 4 x 6.312 4 x 6.3 12 4 x 6.312 apll/8 50 0.50 13.000 2 x 13 apll/8 50 0.50 15.360 3 x 10.24 apll/8 50 0.50 15.552 oc1-oc3 only 77.76 apll/20 50 0.50
________________________________________________________________________________________ ds 3104-se 43 t0 apll t4 apll jitter (typ) frequency (mhz) t0freq t4ft0 t4freq ofreqn rms (ps) pk-pk (ns) 16.000 not oc6, oc7 4 x 10 apll/10 50 0.50 16.384 not oc6 from dig2 dig1,dig2 100 1.00 16.384 12 x e1 apll/6 50 0.50 16.384 16 x e1 16 x e1 16 x e1 apll/8 50 0.50 16.832 4 x 6.312 apll/6 50 0.50 17.184 2 x e3 apll/16 50 0.50 18.528 24 x ds1 24 x ds 1 24 x ds1 apll/8 50 0.50 19.440 not oc6 dig2 100 1.00 19.440 77.76 77.76 apll/16 50 0.50 20.000 4 x 10 apll/8 50 0.50 20.800 oc2, oc3, oc6, oc7 only 2 x 13 apll/5 50 0.50 22.368 ds3 apll/8 50 0.50 24.576 12 x e1 12 x e1 12 x e1 apll/4 50 0.50 24.576 oc2, oc3, oc6, oc7 onl y 3 x 10.24 apll/5 50 0.50 24.704 24 x ds1 apll/6 50 0.50 24.704 16 x ds1 16 x ds 1 16 x ds1 apll/4 50 0.50 25.000 not oc6, oc7 gbe 16 gbe 16 apll/10 50 0.50 25.248 4 x 6.312 4 x 6.3 12 4 x 6.312 apll/4 50 0.50 25.920 77.76 apll/12 50 0.50 26.000 2 x 13 apll/4 50 0.50 30.720 3 x 10.24 apll/4 50 0.50 31.104 not oc6, oc7 77.76 apll/10 50 0.50 31.250 gbe 16 gbe 16 gbe 16 apll/8 50 0.50 31.250 oc1,oc4,oc5 from t0 apll2 apll/10 50 0.50 32.000 oc2, oc3, oc6, oc7 only 4 x 10 apll/5 50 0.50 32.768 16 x e1 16 x e1 16 x e1 apll/4 50 0.50 34.368 2 x e3 apll/8 50 0.50 37.056 24 x ds1 24 x ds 1 24 x ds1 apll/4 50 0.50 38.880 77.76 77.76 apll/8 50 0.50 40.000 4 x 10 apll/4 50 0.50 44.736 ds3 apll/4 50 0.50 49.152 not oc1-oc3 from t0 apll not oc1, oc2 from t4 apll 12 x e1 12 x e1 12 x e1 apll/2 50 0.50 49.408 not oc1-oc3 from t0 apll not oc1, oc2 from t4 apll 16 x ds1 16 x ds1 16 x ds1 apll/2 50 0.50 50.000 oc2, oc3, oc6, oc7 only gbe 16 gbe 16 apll/5 50 0.50 50.496 not oc1-oc3 from t0 apll not oc1, oc2 from t4 apll 4 x 6.312 4 x 6.312 4 x 6.312 apll/2 50 0.50 51.840 77.76 apll/6 60 0.6 52.000 not oc1, oc2 2 x 13 apll/2 50 0.50 61.440 not oc1, oc2 3 x 10.24 apll/2 50 0.50 62.208 oc2, oc3, oc6, oc 7 only 77.76 apll/5 50 0.50 62.500 gbe 16 gbe 16 gbe 16 apll/4 50 0.50 62.500 oc1, oc6, oc7 from t0 apll2 apll/5 50 0.50 65.536 not oc1-oc3 from t0 apll not oc1, oc2 from t4 apll 16 x e1 16 x e1 16 x e1 apll/2 50 0.50 68.736 2 x e3 apll/4 50 0.50 74.112 not oc1-oc3 from t0 apll not oc1, oc2 from t4 apll 24 x ds1 24 x ds1 24 x ds1 apll/2 50 0.50 77.76 77.76 77.76 apll/4 50 0.50 80.000 not oc1, oc2 4 x 10 apll/2 50 0.50 89.472 not oc1, oc2 ds3 apll/2 50 0.50 98.304 not oc1-oc3 from t0 apll oc6, oc7 only from t4 apll 12 x e1 12 x e1 12 x e1 apll/1 50 0.50 98.816 not oc1-oc3 from t0 apll oc6, oc7 only from t4 apll 16 x ds1 16 x ds1 16 x ds1 apll/1 50 0.50 100.992 not oc1-oc3 from t0 apll oc6, oc7 only from t4 apll 4 x 6312 khz 4 x 6312 khz 4 x 6312 khz apll/1 50 0.50 104.000 oc6, oc7 only 2 x 13 apll/1 50 0.50
________________________________________________________________________________________ ds 3104-se 44 t0 apll t4 apll jitter (typ) frequency (mhz) t0freq t4ft0 t4freq ofreqn rms (ps) pk-pk (ns) 122.880 oc6, oc7 only 3 x 10.24 apll/1 50 0.50 125.000 not oc1-oc3 from t0 apll not oc1, oc2 from t4 apll gbe 16 gbe 16 gbe 16 apll/2 50 0.50 131.072 not oc1-oc3 from t0 apll oc6, oc7 only from t4 apll 16 x e1 16 x e1 16 x e1 apll/1 50 0.50 137.472 oc6, oc7 only 2 x e3 apll/2 50 0.50 148.224 not oc1-oc3 from t0 apll oc6, oc7 only from t4 apll 24 x ds1 24 x ds1 24 x ds1 apll/1 50 0.50 155.520 not oc1-oc3 from t0 apll not oc1, oc2 from t4 apll 77.76 77.76 apll/2 60 0.6 156.250 oc4-oc7 only from t0 apll2 apll/2 50 0.50 160.000 oc6, oc7 only 4 x 10 apll/1 50 0.50 178.944 oc6, oc7 only ds3 apll/1 50 0.50 250.000 oc4-oc7 only gbe 16 apll/1 50 0.50 274.944 oc6, oc7 only 311.040 oc4-oc7 only 77.76 apll/1 50 0.50 312.500 oc4-oc7 only from t0 apll2 apll/2 50 0.50 7.8.2.4 fsync and mfsy nc configuration the fsync output is enabled by setting fsen = 1 in the ocr4 register, while the mfsync output is enabled by setting mfsen = 1 in ocr4 . when disabled, these pins are driven low. when 8kpul = 0 in fscr1 , fsync is configured as an 8khz cloc k with 50% duty cycle. when 8kpul = 1, fsync is an 8khz frame sync that pulses low once every 125 s with pulse width equal to one cycle of output clock oc3. when 8kinv = 1 in fscr1 , the clock or pulse polarity of fsync is inverted. when 2kpul = 0 in fscr1 , mfsync is configured as an 2khz clo ck with 50% duty cycle. when 2kpul = 1, mfsync is a 2khz frame sync that pulses low once every 500 s with pulse width equal to one cycle of output clock oc3. when 2kinv = 1 in fscr1 , the clock or pulse polarity f mfsync is inverted. if either 8kpul = 1 or 2kpul = 1, then output clock oc3 must be generated from the t0 dpll and must be configured for a frequency of 1.544mhz or higher or the fsync/mfsync pulses may not be generated correctly. figure 7-4 shows how the 8kpul and 8kinv control bits affe ct the fsync output. the 2kpul and 2kinv bits have an identical effect on mfsync. figure 7-4. fsync 8khz options oc3 output clock fsync, 8kpul=0, 8kinv=0 fsync, 8kpul=0, 8kinv=1 fsync, 8kpul=1, 8kinv=0 fsync, 8kpul=1, 8kinv=1
________________________________________________________________________________________ ds 3104-se 45 7.8.2.5 custom output frequencies in addition to the many standard frequencies available in the device, any of the se ven output dfs blocks can be configured to generate a custom frequency. possible cu stom frequencies include any multiple of 2khz up to 77.76mhz and any multiple of 8khz up to 311.04mhz. (an apll must be used to achieve frequencies above 77.76mhz.) any of the programmable output clocks can be configured to output the custom frequency or submultiples thereof. contact the factory at telecom.support@dalsemi.com for help with custom frequencies. 7.9 frame and multiframe alignment in addition to receiving and locking to clocks such as 19 .44mhz from system timing cards, the DS3104-se can also receive and align its outputs to 2khz mult iframe sync or 8khz frame sync signals from system timing cards. in this mode of operation, both a higher speed clock (such as 6. 48mhz or 19.44mhz) and a fr ame (or multiframe) sync signal from each timing card are passed to the line card s. the higher speed clock from each timing card is connected to a regular input clock pin on the DS3104-se, su ch as ic3 or ic4, while the frame sync signal is connected to a syncn input pin on the DS3104-se, su ch as sync1 or sync2. the DS3104-se locks to the higher speed clock from one of the timing cards and sample s the frame sync signal on the associated syncn pin. the DS3104-se then uses the syncn signal to falling-edge alig n some or all of the output clocks. only the falling edge of the syncn signal has significance. a 4khz or 8khz clock can also be used on the syncn pins without any changes to the register conf iguration, but only output clocks of 8khz and above are aligned in this case. phase build-out should be disabled (pboen = 0 in mcr10 ) when using syncn signals. when fscr3. source! = 11xx, the frame sync signal ca n only come from the sync1 pin. when fscr3. source = 11xx, the frame sync signal comes fr om one of sync1, sync2, or sync3. see section 7.9.3 . 7.9.1 sampling by default the syncn signal is first sampled on the rising edge of the selected reference. this gives the most margin, given that the syncn signal is falling-edge aligne d with the selected reference since both come from the same timing card. the expected timing of the syncn signal with respect to the sampling clock can be adjusted from 0.5 cycles early to 1 cycle late using the fscr2 :phasen[1:0] field. 7.9.2 resampling the syncn signal is then resampled by an internal clock der ived from the t0 dpll. the resampling resolution is a function of the frequency of the selected reference and fscr2 :ocn. when ocn = 0, the resampling resolution is 6.48mhz, which gives the highest sampling margin and also aligns clocks at 6.48mhz and multiples thereof. when ocn = 1, if the selected reference is 19.44mhz the resa mpling resolution is 19.44mhz. if the selected reference is 38.88 mhz the resampling resolution is 38.88mhz. the selected reference must be either 19.44mhz or 38.88mhz. 7.9.3 enable the syncn signal is only allowed to align output clocks if the t0 dpll is locked and the syncn signal is enabled and qualified. when fscr3 :source[3:0]! = 11xx, external frame sync on the sync1 pin can be enabled automatically or manually. when mcr3 :aefsen = 1, external frame sync is enabled automatically when efsen = 1 and the t0 dpll is locked to the input clock specified by fscr3 :source[3:0]. when aefsen = 0, external frame sync is enabled manually when mcr3 :efsen = 1 and disabled when efsen = 0. in manual mode when efsen = 1, fscr3 :source[3:0] is ignored and external frame sync is al ways enabled regardless of which input clock is the selected reference. when fscr3 :source[3:0] = 11xx, external frame sync from the syncn pins can be enabled when efsen = 1 and the associated input clock becomes the selected reference. mcr3 :aefsen can be used to automatically disable efsen when the selected reference changes. see section 7.9.7 .
________________________________________________________________________________________ ds 3104-se 46 7.9.4 qualification the syncn signal is qualified when it has consistent phas e and correct frequency. specifically, it is qualified when its significant edge has been found at exact 2khz boundaries (when resampled as described above) for 64 cycles in a row. it is disqualified when one significant edge is not found at the 2khz boundary. if there is no syncn signal or a bad syncn signal, and external frame sync is enabled, the syncn signal will never get qualified and the 2khz output will simply free-run at its current 2khz alignment. 7.9.5 output clock alignment when the t0 dpll is locked, external frame sync is enabl ed and the syncn signal is qualified, the syncn signal can be used to falling-edge align th e t0 dpll derived output clocks. out put clocks fsync and mfsync share a 2khz alignment generator, while the rest of the t0 dpll derived output clocks share a second 2khz alignment generator. when external frame sync is not enabled or the syncn signal is not qualified, these 2hz alignment generators free-run with their existing 2khz alignments. when external frame sync is enabled and the syncn signal is qualified, the fsync/mfsync 2khz alignment generator is always synchronized by syncn, and therefore fsync and mfsync are always falling-edge aligned with syncn. when fscr2 :indep = 0, the t0 dpll 2khz alignment generator is also synchronized with the fsync/mfsync 2khz alignment generator to falling-edge align all t0-derived output clocks with syncn. when indep = 1, the t0 dpll 2-khz alignment generator is not synchronized with the fsync/mfsync 2khz alignm ent generator and continues to free-run with its existing 2khz alignment. this av oids any disturbance on the t0 dpll derived output clocks when syncn has a change of phase position. 7.9.6 frame sync monitor the frame sync monitor signal opstate :fsmon operates in two modes, depending on the setting of the enable bit ( mcr3 :efsen). when efsen = 1 (external frame sync enabled) the opstate :fsmon bit is set when syncn is not qualified and cleared when syncn is qualified. if syncn is disqualifi ed then both 2khz alignment generators are immediately disconnected from syncn to avoid phase movement on the t0-derived outputs clocks. when opstate :fsmon is set, the latched status bit msr3 :fsmon is also set, which can c ause an interrupt if enabled in the ier3 register. if syncn immediately stabilizes at a new phase and proper frequency, then it is requa lified after 64 2khz cycles (nominally 32ms). unless system softw are intervenes, after syncn is requa lified the 2khz alignment generators will synchronize with syncn?s new phase alignment, causing a sudden phase movement on the output clocks. system software can avoid this sudden phase movement on the output clocks by responding to the fsmon interrupt within the 32ms window with appropriate action, which might include disabling external frame sync ( mcr3 :efsen = 0) to prevent the resynchronization of the 2khz alignment generators with syncn, forcing the t0 dpll into holdover ( mcr1 :t0state = 010) to avoid affecting the out put clocks with any other phase hits, and possibly even disabling the master timing card and promoti ng the slave timing card to master since the 2khz signal from the master should not have such phase movements. when efsen = 0 (external frame sync disabled) opstate :fsmon is set when the negative edge of the re- sampled syncn signal is outside of the window determined by fscr3 :monlim relative to the mfsync negative edge (or positive edge if mfsync is inverted) and clear when within the window. when opstate :fsmon is set, the latched status bit msr3 :fsmon is also set, which can cause an interrupt if enabled in the ier3 register. 7.9.7 syncn pins the external frame sync signal can be automatically selected from one to three separate sync[1:3] pins depending on the setting of fscr1 :syncsrc[2:0] and which input clock is the t0 dpll selected reference. if no associated input pin is selected as the t0 dpll input reference, the internal syncn signal is inactive and will not be qualified. this function is enabled by setting fscr3 .source = 11xx.
________________________________________________________________________________________ ds 3104-se 47 table 7-15. external frame sync source syncsrc[2:0] selected reference external frame sync source ic3 or ic5 sync1 ic4 or ic6 sync2 0xx ic9 or ic2 sync3 ic3 sync1 1x0 ic4 sync2 10x ic9 sync3 ic5 sync1 1x1 ic6 sync2 11x ic2 sync3 there are three phasen[1:0] (n = 1, 2, 3) select fields in the fscr2 register. phase1[1:0] is associated with sync1, phase2[1:0] is associated with sync2, and ph ase3[1:0] is associated with sync3. all three syncn inputs can have their timing adjusted to account for frame sy nc signal vs. clock signal delay differences in each path. when this function is enabled with fscr3 .source = 11xx, mcr3 .aefsen, and mcr3 .efsen, the monitoring and qualification function described in section 7.9.4 is only performed on the selected syncn input pin. 7.9.8 other confi guration options fsync and mfsync are always produced from the t0 dp ll. output clocks oc1 to oc7 can also be configured as 2khz or 8khz outputs, derived from either the t0 dp ll or the t4 dpll (as specified by the 2k8ksrc bit in fscr1 ). if needed, the t4 dpll can be used as a separate dp ll for the frame sync path by configuring it for a 2khz input and 2khz and/or 8khz frame sync outputs. 7.10 microprocessor interface the device presents an spi interface on the cs , sclk, sdi, and sdo pins. spi is a widely used master/slave bus protocol that allows a master device and one or more slave devices to communicate over a serial bus. the DS3104-se is always a slave device. ma sters are typically microprocessors, asics or fpgas. data transfers are always initiated by the master device, which also gener ates the sclk signal. the DS3104-se receives serial data on the sdi pin and transmits serial data on the sdo pin. sdo is high impedance except when the DS3104-se is transmitting data to the bus master. bit order. when both bit 3 and bit 4 are low at device address 3fffh, the register address and all data bytes are transmitted msb first on both sdi and sdo. when either bi t 3 or bit 4 is set to 1 at device address 3fffh, the register address and all data bytes are transmitted lsb first on both sdi and sdo. the reset default setting and motorola spi convention is msb first. clock polarity and phase. the cpol pin defines the polarity of sclk . when cpol = 0, sclk is normally low and pulses high during bus transactions. when cpol = 1, sclk is normally high and pulses low during bus transactions. the cpha pin sets the phase (active edge) of sclk. when cpha = 0, data is latched in on sdi on the leading edge of the sclk pulse and updated on sdo on t he trailing edge. when cpha = 1, data is latched in on sdi on the trailing edge of the sclk pulse and updated on sdo on the following leading edge. sclk does not have to toggle between access, i.e., when cs is high. see figure 7-5 . device selection. each spi device has its own chip-select line. to select the DS3104-se, pull its cs pin low. control word. after cs is pulled low, the bus master transmits th e control word during the first sixteen sclk cycles. in msb-first mode the control word has the form: r/ w a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 burst
________________________________________________________________________________________ ds 3104-se 48 where a[13:0] is the register address, r/ w is the data direction bit (1 = read, 0 = write), and burst is the burst bit (1 = burst access, 0 = single-byte access). in lsb-first mode the order of the 14 address bits is reversed. in the discussion that follows, a control word with r/ w = 1 is a read control word, while a control word with r/ w = 0 is a write control word. single-byte writes. see figure 7-6 . after cs goes low, the bus master transmit s a write control word with burst = 0 followed by the data byte to be written. the bu s master then terminates the transaction by pulling cs high. single-byte reads. see figure 7-6 . after cs goes low, the bus master transmit s a read control word with burst = 0. the DS3104-se then responds with the requested data byte. the bus master then terminates the transaction by pulling cs high. burst writes. see figure 7-6 . after cs goes low, the bus master transmits a write control word with burst = 1 followed by the first data byte to be written. the DS3104-se receives the first data byte on sdi, writes it to the specified register, increments its inte rnal address register, and prepares to receive the next data byte. if the master continues to transmit, the DS3104-se continues to write t he data received and incremen t its address counter. after the address counter reaches 3fffh it rolls over to address 0000h and continues to increment. burst reads. see figure 7-6 . after cs goes low, the bus master transmits a read control word with burst = 1. the DS3104-se then responds with the requested data by te on sdo, increments its address counter, and prefetches the next data byte. if the bus master continues to demand data, the DS3104-se continues to provide the data on sdo, increment its address counter, and prefetch the following byte. after the address counter reaches 3fffh it rolls over to address 0000h and continues to increment. early termination of bus transactions. the bus master can terminate spi bus transactions at any time by pulling cs high. in response to early terminations, the DS3104- se resets its spi interface logic and waits for the start of the next transaction. if a write transaction is terminated prior to t he sclk edge that latches the lsb of a data byte, the data byte is not written. design option: wiring sdi and sdo together. because communication between the bus master and the DS3104-se is half-duplex, the sdi and sdo pins can be wired together externally to reduce wire count. to support this option, the bus master must not drive t he sdi/sdo line when the DS3104-se is transmitting. ac timing. see table 10-10 and figure 10-4 for ac timing specifications for the spi interface.
________________________________________________________________________________________ ds 3104-se 49 figure 7-5. spi clock phase options msb lsb 654321 cs sclk sdi/sdo clock edge used for data capture (all modes) cpol = 0, cpha = 0 cpol = 0, cpha = 1 cpol = 1, cpha = 0 cpol = 1, cpha = 1 sclk sclk sclk
________________________________________________________________________________________ ds 3104-se 50 figure 7-6. spi bus transactions r/ w register address burst data byte sdi cs sdo single-byte write single-byte read r/ w register address burst data byte r/ w register address burst data byte 1 burst write sdi cs sdo sdi cs sdo 0 (write) 0 (single-byte) 1 (read) 0 (single-byte) 0 (write) 1 (burst) data byte n r/ w register address burst data byte 1 burst read sdi cs 1 (read) 1 (burst) data byte n
________________________________________________________________________________________ ds 3104-se 51 7.11 reset logic the device has three reset controls: the rst pin, the rst bit in mcr1 , and the jtag reset pin jtrst . the rst pin asynchronously resets the entire device , except for the jtag logic. when the rst pin is low all internal registers are reset to their default values, including those fields which latch their default values from, or based on, the states of configurat ion input pins when the rst goes high. the rst pin must be asserted once after power- up while the external oscillator is stabilizing. the mcr1 :rst bit resets the entire device (except for the mi croprocessor interface, the jtag logic, and the rst bit itself), but when rst is active, the register fields with pin-programmed defaults do not latch their values from, or based on, the corresponding input pins. instead these fields are reset to the default values that were latched when the rst pin was last active. maxim recommends holding rst low while the external oscillator starts up and stabilizes. an incorrect reset condition could result if rst is released before the oscilla tor has started up completely. important: system software must wait at least 100s after reset ( rst pin or rst bit) is deasserted before initializing the device as described in section 7.13 . 7.12 power-supply considerations due to the dual-power-supply nature of the DS3104-se, some i/os have parasitic di odes between a 1.8v supply and a 3.3v supply. when ramping power supplies up or do wn, care must be taken to avoid forward-biasing these diodes because it could cause latchup. two methods are ava ilable to prevent this. the first method is to place a schottky diode external to the device between the 1.8v suppl y and the 3.3v supply to force the 3.3v supply to be less than one parasitic diode drop below the 1.8v supply. the second method is to ramp up the 3.3v supply first and then ramp up the 1.8v supply. 7.13 initialization after power-up or reset, a series of writes must be done to the DS3104-se to tune it for optimal performance. this series of writes is called the initia lization script. each die revision of the DS3104-se has a different initialization script. download the latest initialization scripts from the DS3104-se web page at www.maxim-ic.com/DS3104-se , or email telecom.support@dalsemi.com .
________________________________________________________________________________________ ds 3104-se 52 8. register descriptions the DS3104-se has an overall address range from 000h to 1ffh. table 8-1 in section 8.4 shows the register map. in each register, bit 7 is the msb and bit 0 is the lsb. register addresses not listed and bits marked ??? are reserved and must be written with 0. writing other values to these registers may put the device in a factory test mode resulting in undefined operation. bits labeled ?0? or ?1 ? must be written with that value for proper operation. register fields with underlined names are read-only fields; writes to thes e fields have no effect. all other fields are read-write. register fields are described in det ail in the register descriptions that follow table 8-1 . 8.1 status bits the device has two types of status bits. real-time status bits are read-only and indicate the state of a signal at the time it is read. latched status bits are set when a signal changes state (low-to-high, hi gh-to-low, or both, depending on the bit) and cleared when written with a logic 1 value. wr iting a 0 has no effect. when set, some latched status bits can cause an interrupt request on the intreq pin if enabled to do so by corresponding interrupt enable bits. isr#.lock# are special-case latched status bits becaus e they cannot create an inte rrupt request on the intreq pin and a ?write 0? is needed to clear them. 8.2 configuration fields configuration fields are read-write. du ring reset, each configuration field reverts to the default value shown in the register definition. configuration register bits marked ??? are reserved and must be written with 0. 8.3 multiregister fields multiregister fields?such as freq[18:0] in registers freq1 , freq2 and freq3 ?must be handled carefully to ensure that the bytes of the field remain consistent. a write access to a multiregister field is accomplished by writing all the registers of the field in any order, with no other accesses to the device in between. if the write sequence is interrupted by another access, none of the bytes are written and the msr4 :mraa latched status bit is set to indicate the write was aborted. a read access fr om a multiregister field is accomplished by reading the registers of the field in any order, with no other acce sses to the device in betw een. when one register of a multiregister field is read, the other register(s) in the field are frozen until after they are all read. if the read sequence is interrupted by another access, the regi sters of the multibyte field are unfrozen and the msr4 :mraa bit is set to indicate the read was aborted. for best results, interrupt servicin g should be disabled in the microprocessor before a multiregiste r access and then enabled again after the access is complete. the multiregister fields are: field registers addresses type freq[18:0] freq1 , freq2 , freq3 07, 0c, 0d read-only mclkfreq[15:0] mclk1 , mclk2 3c, 3d read/write hardlim[9:0] dlimit1 , dlimit2 41, 42 read/write divn[15:0] divn1 , divn2 46, 47 read/write offset[15:0] offset1 , offset2 70, 71 read/write phase[15:0] phase1 , phase2 77, 78 read-only
________________________________________________________________________________________ ds 3104-se 53 8.4 register definitions table 8-1. register map note: register names are hyperlinks to register definitions. underlined fields are read-only. addr register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h id1 id[7:0] 01 id2 id[15:8] 02 rev rev[7:0] 03 test1 palarm d180 ? ra 0 8kpol 0 0 05 msr1 ic8 ? ic6 ic5 ic4 ic3 ic2 ic1 06 msr2 state srfail ? ? ? ? ? ic9 07 freq3 ? ? ? ? ? freq[18:16] 08 msr3 fsmon t4lock ? t4noin ? ? ? ? 09 opstate fsmon t4lock t0soft t4soft ? t0state[2:0] 0a ptab1 ref1[3:0] selref[3:0] 0b ptab2 ref3[3:0] ref2[3:0] 0c freq1 freq[7:0] 0d freq2 freq[15:8] 0e valsr1 ic8 ? ic6 ic5 ic4 ic3 ic2 ic1 0f valsr2 ? hordy ? ? ? ? ? ic9 10 isr1 ? ? act2 lock2 ? ? act1 lock1 11 isr2 ? ? act4 lock4 ? ? act3 lock3 12 isr3 ? ? act6 lock6 ? ? act5 lock5 13 isr4 ? ? act8 lock8 ? ? ? ? 14 isr5 ? ? ? ? ? ? act9 lock9 17 msr4 ? hordy mraa ? ? ? ? ? 18 ipr1 pri2[3:0] pri1[3:0] 19 ipr2 pri4[3:0] pri3[3:0] 1a ipr3 pri6[3:0] pri5[3:0] 1b ipr4 pri8[3:0] ? 1c ipr5 ? pri9[3:0] 20 icr1 divn lock8k bucket[1:0] freq[3:0] 21 icr2 divn lock8k bucket[1:0] freq[3:0] 22 icr3 divn lock8k bucket[1:0] freq[3:0] 23 icr4 divn lock8k bucket[1:0] freq[3:0] 24 icr5 divn lock8k bucket[1:0] freq[3:0] 25 icr6 divn lock8k bucket[1:0] freq[3:0] 27 icr8 divn lock8k bucket[1:0] freq[3:0] 28 icr9 divn lock8k bucket[1:0] freq[3:0] 30 valcr1 ic8 ? ic6 ic5 ic4 ic3 ic2 ic1 31 valcr2 ? ? ? ? ? ? ? ic9 32 mcr1 rst ? fren lockpin ? t0state[2:0] 33 mcr2 ? ? ? ? t0force[3:0] 34 mcr3 aefsen lkato xoedge manho efsen sonsdh ? revert 35 mcr4 lkt4t0 ? ? ? t4force[3:0] 36 mcr5 rsv4 rsv3 rsv2 rsv1 ic2sf ic1sf ic6sf ic5sf 37 ocr6 ? oc5en oc4en oc5ben oc4ben oc3ben oc2ben oc1ben 38 mcr6 dig2af dig2ss dig1ss ? ? ? ? ? 39 mcr7 dig2f[1:0] dig1f[1:0] ? ? dig2src dig1src
________________________________________________________________________________________ ds 3104-se 54 addr register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3a mcr8 oc5sf oc4sf oc7sf oc6sf 3b mcr9 autobw ? ? ? limint ? ? ? 3c mclk1 mclkfreq[7:0] 3d mclk2 mclkfreq[15:8] 40 hocr3 avg ? ? ? ? 41 dlimit1 hardlim[7:0] 42 dlimit2 ? ? ? ? ? ? hardlim[9:8] 43 ier1 ic8 ? ic6 ic5 ic4 ic3 ic2 ic1 44 ier2 state srfail ? ? ? ? ? ic9 45 ier3 fsmon t4lock ? t4noin ? ? ? ? 46 divn1 divn[7:0] 47 divn2 divn[15:0] 48 mcr10 ? srfpin ufsw extsw pbofrz pboen ? ? 4b mcr11 ? ? ? t4t0 ? ? ? ? 4d dlimit3 fllol softlim[6:0] 4e ier4 ? hordy ? ? ? ? ? ? 4f ocr5 ? aof7 aof6 aof5 aof4 aof3 aof2 aof1 50 lb0u lb0u[7:0] 51 lb0l lb0l[7:0] 52 lb0s lb0s[7:0] 53 lb0d ? ? ? ? ? ? lb0d[1:0] 54 lb1u lb1u[7:0] 55 lb1l lb1l[7:0] 56 lb1s lb1s[7:0] 57 lb1d ? ? ? ? ? ? lb1d[1:0] 58 lb2u lb2u[7:0] 59 lb2l lb2l[7:0] 5a lb2s lb2s[7:0] 5b lb2d ? ? ? ? ? ? lb2d[1:0] 5c lb3u lb3u[7:0] 5d lb3l lb3l[7:0] 5e lb3s lb3s[7:0] 5f lb3d ? ? ? ? ? ? lb3d[1:0] 60 ocr1 ofreq2[3:0] ofreq1[3:0] 61 ocr2 ofreq4[3:0] ofreq3[3:0] 62 ocr3 ofreq6[3:0] ofreq5[3:0] 63 ocr4 mfsen fsen ? ? ofreq7[3:0] 64 t4cr1 ? ? ? ? t4freq[3:0] 65 t0cr1 t4mt0 t4apt0 t0ft4[2:0] t0freq[2:0] 66 t4bw ? ? ? ? ? ? t4bw[1:0] 67 t0lbw ? ? ? rsv1 t0lbw[3:0] 69 t0abw ? ? ? rsv1 t0abw[3:0] 6a t4cr2 ? pd2g8k[2:0] ? damp[2:0] 6b t0cr2 ? pd2g8k[2:0] ? damp[2:0] 6c t4cr3 pd2en ? pd2g[2:0] 6d t0cr3 pd2en ? pd2g[2:0] 6e gpcr gpio4d gpio3d gpio2d gpio1d gpio4o gpio3o gpio2o gpio1o 6f gpsr ? ? ? ? gpio4 gpio3 gpio2 gpio1 70 offset1 offset[7:0] 71 offset2 offset[15:8]
________________________________________________________________________________________ ds 3104-se 55 addr register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 72 pboff ? ? pboff[5:0] 73 phlim1 flen nalol 1 ? ? finelim[2:0] 74 phlim2 clen mcpden usemcpd ? coarselim[3:0] 76 phmon nw ? ? ? ? 77 phase1 phase[7:0] 78 phase2 phase[15:8] 79 phlkto phlktom[1:0] phlkto[5:0] 7a fscr1 2k8ksrc syncsrc 8kinv 8kpul 2kinv 2kpul 7b fscr2 indep ocn phase3[1:0] phase2[1:0] phase1[1:0] 7c fscr3 recal monlim[2:0] source[3:0] 7d intcr ? ? ? ? los gpo od pol 7e prot prot[7:0] register map color coding device identification and protection local oscillator and master clock configuration input clock configuration input clock monitoring input clock selection dpll configuration dpll state output clock configuration frame/multiframe sync configuration
________________________________________________________________________________________ ds 3104-se 56 register name: id1 register description: device identification register, lsb register address: 00h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name id[7:0] default 0 0 1 0 0 0 0 0 bits 7 to 0: device id (id[7:0]). id[15:0] = 0c20h = 3104 decimal. register name: id2 register description: device identification register, msb register address: 01h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name id[15:8] default 0 0 0 0 1 1 0 0 bits 7 to 0: device id (id[15:8]). see the id1 register description. register name: rev register description: device revision register register address: 02h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name rev[7:0] default 0 0 0 0 0 0 0 0 bits 7 to 0: device revision (rev[7:0]). contact the factory to interpret this value and determine the latest revision.
________________________________________________________________________________________ ds 3104-se 57 register name: test1 register description: test register 1 (not normally used) register address: 03h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name palarm d180 ? ra 0 8kpol 0 0 default 0 0 0 1 0 1 0 0 bit 7: phase alarm (palarm). this real-time status bit indicates the st ate of the t0 dpll phase lock detector. see section 7.7.6 . ( note: this is not the same as t0state = locked.) 0 = t0 dpll phase-lock parameters are met (flen, clen, nalol, fllol) 1 = t0 dpll loss of phase lock bit 6: disable 180 (d180). when locking to a new reference, the t0 dpll first tries nearest-edge locking ( 180 ) for the first two seconds. if unsuccessful it then tries full phase/frequency locking ( 360 ). disabling the nearest- edge locking can reduce lock time by up to two seco nds but may cause an unnecessary phase shift (up to 360 ) when the new reference is close in frequency /phase to the old reference. see section 7.7.5 . 0 = normal operation: try nearest-edge locking then phase/frequency locking 1 = phase/frequency locking only bit 4: resync analog dividers (ra). when this bit is set the analog output dividers are always synchronized to ensure that low-frequency outputs are in sync with the higher frequency clock from the dpll. 0 = synchronized for the first two seconds after power-up 1 = always synchronized bits 3, 1, and 0: leave set to zero (test control). bit 2: 8khz edge polarity (8kpol). specifies the input clock edge to lock to on the selected reference when it is configured for lock8k mode. see section 7.4.2 . 0 = falling edge 1 = rising edge
________________________________________________________________________________________ ds 3104-se 58 register name: msr1 register description: master status register 1 register address: 05h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ic8 ? ic6 ic5 ic4 ic3 ic2 ic1 default 1 0 1 1 1 1 1 1 bits 7 and 5 to 0: input clock status change (ic8 and ic[6:1]). each of these latched status bits is set to 1 when the corresponding valsr1 status bit changes state (set or cleared). each bit is cleared when written with a 1 and not set again until the valsr1 bit changes state again. when one of th ese latched status bits is set it can cause an interrupt request on the intreq pin if the corresponding interrupt enable bit is set in the ier1 register. see section 7.5 for input clock validation/invalidation criteria. register name: msr2 register description: master status register 2 register address: 06h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name state srfail ? ? ? ? ? ic9 default 0 0 0 0 0 0 0 1 bit 7: t0 dpll state change (state). this latched status bit is set to 1 wh en the operating state of the t0 dpll changes. state is cleared when written with a 1 and not set again until the operating state changes again. when state is set it can cause an interrupt request on the in treq pin if the state interrupt enable bit is set in the ier2 register. the current operating state ca n be read from the t0state field of the opstate register. see section 7.7.1 . bit 6: selected reference failed (srfail). this latched status bit is set to 1 when the selected reference to the t0 dpll fails, (i.e., no clock edges in two ui). srfail is cleared when written wi th a 1. when srfail is set it can cause an interrupt request on the intreq pin if the srfail interrupt enable bit is set in the ier2 register. srfail is not set in free-run mode or holdover mode. see section 7.5.3 . bit 0: input clock status change (ic9). this latched status bit is set to 1 when the corresponding valsr status bit changes state (set or cleared). each bit is clea red when written with a 1 and not set again until the valsr2 bit changes state again. when this latched status bit is set it can cause an interrupt request on the intreq pin if the corresponding interrupt enable bit is set in the ier2 register. see section 7.5 for input clock validation/invalidation criteria. register name: freq3 register description: frequency register 3 register address: 07h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? ? freq[18:16] default 0 0 0 0 0 0 0 0 bits 2 to 0: current dpll frequency (freq[18:16]). see the freq1 register description.
________________________________________________________________________________________ ds 3104-se 59 register name: msr3 register description: master status register 3 register address: 08h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name fsmon t4lock ? t4noin ? ? ? ? default 0 1 0 1 0 0 0 0 bit 7: frame sync input monitor alarm (fsmon). this latched status bit is set to 1 when opstate :fsmon transitions from 0 to 1. fsmon is cleared when written wi th a 1. when fsmon is set it can cause an interrupt request on the intreq pin if the fsmon interrupt enable bit is set in the ier3 register. see section 7.9 . bit 6: t4 dpll lock status change (t4lock). this latched status bit is set to 1 when the lock status of the t4 dpll ( opstate :t4lock) changes (becomes locked when previ ously unlocked or becomes unlocked when previously locked). t4lock is cleared when written with a 1 and not set again until the t4 lock status changes again. when t4lock is set it can cause an interrupt reque st on the intreq pin if the t4lock interrupt enable bit is set in the ier3 register. see section 7.7.6 . bit 4: t4 no valid inputs alarm (t4noin). this latched status bit is set to 1 when the t4 dpll has no valid inputs available. t4noin is cleared when written with a 1 unless the t4 dpll still has no valid inputs available. when t4noin is set it can cause an interrupt request on the intreq pin if the t4noin interrupt enable bit is set in the ier3 register. see section 7.5 .
________________________________________________________________________________________ ds 3104-se 60 register name: opstate register description: operating state register register address: 09h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name fsmon t4lock t0soft t4soft ? t0state[2:0] default 1 0 0 0 0 0 0 1 bit 7: frame sync input monitor alarm (fsmon). this real-time status bit indicates the current status of the frame sync input monitor. see section 7.9.6 . 0 = no alarm 1 = alarm bit 6: t4 dpll lock status (t4lock). this real-time status bit indicates th e current phase lock status of the t4 dpll. see sections 7.5.3 and 7.7.6 . 0 = not locked to selected reference 1 = locked to selected reference bit 5: t0 dpll frequency soft alarm (t0soft). this real-time status bit indicate s whether or not the t0 dpll is tracking its reference within the soft alarm lim its specified in the soft[6:0] field of the dlimit3 register. see section 7.7.6 . 0 = no alarm; frequency is within the soft alarm limits 1 = soft alarm; frequency is outside the soft alarm limits bit 4: t4 dpll frequency soft alarm (t4soft). this real-time status bit indicate s whether or not the t4 dpll is tracking its reference within the soft alarm lim its specified in the soft[6:0] field of the dlimit3 register. see section 7.7.6 . 0 = no alarm; frequency is within the soft alarm limits 1 = soft alarm; frequency is outside the soft alarm limits bits 2 to 0: t0 dpll operating state (t0state[2:0]). this real-time status field indi cates the current state of the t0 dpll state machine. values not listed below co rrespond to invalid (unused) states. see section 7.7.1 . 001 = free-run 010 = holdover 100 = locked 101 = prelocked 2 110 = prelocked 111 = loss-of-lock
________________________________________________________________________________________ ds 3104-se 61 register name: ptab1 register description: priority table register 1 register address: 0ah bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ref1[3:0] selref[3:0] default 0 0 0 0 0 0 0 0 bits 7 to 4: highest priority valid reference (ref1[3:0]). this real-time status field indicates the highest-priority valid input reference. when t4t0 = 0 in the mcr11 register, this field indicates the highest priority reference for the t0 dpll. when t4t0 = 1, it indicates the highest priority reference for the t4 dpll. note that an input reference cannot be indicated in this field if it has been marked invalid in the valcr1 or valcr2 register. when the t0 dpll is in nonreve rtive mode (revert = 0 in the mcr3 register) this field may not have the same value as the selref[3:0] field. see section 7.6.2 . 0000 = no valid input reference available 0001 = input ic1 0010 = input ic2 0011 = input ic3 0100 = input ic4 0101 = input ic5 0110 = input ic6 0111 = {unused value} 1000 = input ic8 1001 = input ic9 1010 to 1111 = {unused values} bits 3 to 0: selected reference (selref[3:0]). this real-time status field indicates the current selected reference. when t4t0 = 0 in the mcr11 register, this field indicates the selected reference for the t0 dpll. when t4t0 = 1, it indicates the selected reference for the t4 dpll. note that an input clock cannot be indicated in this field if it has been marked invalid in the valcr1 or valcr2 register. when the t0 dpll is in nonrevertive mode (revert = 0 in the mcr3 register) this field may not have the same value as the ref1[3:0] field. see section 7.6.2 . 0000 = no source currently selected 0001 = input ic1 0010 = input ic2 0011 = input ic3 0100 = input ic4 0101 = input ic5 0110 = input ic6 0111 = {unused value} 1000 = input ic8 1001 = input ic9 1010 to 1111 = {unused values}
________________________________________________________________________________________ ds 3104-se 62 register name: ptab2 register description: priority table register 2 register address: 0bh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ref3[3:0] ref2[3:0] default 0 0 0 0 0 0 0 0 bits 7 to 4: third highest priority valid reference (ref3[3:0]). this real-time status field indicates the third highest priority validated input reference. when t4t0 = 0 in the mcr11 register, this field indicates the third highest priority reference for the t0 dpll. when t4t0 = 1, it indicates the third highest reference for the t4 dpll. note that an input reference cannot be indicated in this field if it has been marked invalid in the valcr1 or valcr2 register. see section 7.6.2 . 0000 = less than three valid sources available 0001 = input ic1 0010 = input ic2 0011 = input ic3 0100 = input ic4 0101 = input ic5 0110 = input ic6 0111 = {unused value} 1000 = input ic8 1001 = input ic9 1010 to 1111 = {unused values} bits 3 to 0: second highest priority valid reference (ref2[3:0]). this real-time status field indicates the second highest priority validated input reference. when t4t0 = 0 in the mcr11 register, this field indicates the second highest priority reference for the t0 dpll. when t4 t0 = 1, it indicates the second highest reference for the t4 dpll. note that an input reference cannot be indicated in this field if it has been marked invalid in the valcr1 or valcr2 register. see section 7.6.2 . 0000 = less than two valid sources available 0001 = input ic1 0010 = input ic2 0011 = input ic3 0100 = input ic4 0101 = input ic5 0110 = input ic6 0111 = {unused value} 1000 = input ic8 1001 = input ic9 1010 to 1111 = {unused values}
________________________________________________________________________________________ ds 3104-se 63 register name: freq1 register description: frequency register 1 register address: 0ch bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name freq[7:0] default 0 0 0 0 0 0 0 0 note: the freq1, freq2, and freq3 registers must be read consecutively. see section 8.3 . bits 7 to 0: current dpll frequency (freq[7:0]). the full 19-bit freq[18:0] field spans this register, freq2 and freq3. freq is a two?s-complement signed integer that expresses the current frequency as an offset with respect to the master clock frequency (see section 7.3 ). when t4t0 = 0 in the mcr11 register, freq indicates the current frequency offset of the t0 dpll. when t4t0 = 1, freq indicate s the current frequency offset of the t4 path. because the value in this register field is der ived from the dpll integral path, it can be considered an average frequency with a rate of change inversely proportional to the dpll bandwidth. if limint = 1 in the mcr9 register, the value of freq freezes when the dpll re aches its minimum or maximum frequency. the frequency offset in ppm is equal to freq[18:0] x 0.0003068. see section 7.7.1.6 . application note: frequency measurements are relative, i.e., they measure the frequency of the selected reference with respect to the local oscillator. as such, when a frequenc y difference exists, it is difficult to distinguish whether the selected reference is off frequency or the local o scillator is off frequency. in systems with timing card redundancy, the use of two timing cards, master and slave, can address this difficulty. both master and slave have separate local oscillators, and each measures the selected reference. these two measurements provide the necessary information to distinguish which reference is off frequency, if we make the simple assumption that at most one reference has a significant frequency deviation at any given time (i.e., a single point of failure). if both master and slave indicate a significant frequency offset, then the selected reference must be off frequency. if the master indicates a frequency offset but the slave does no t, then the master?s local oscillator must be off frequency. likewise, if the slave indicates a frequency offset but the master does not, then slave?s local oscillator must be off frequency. register name: freq2 register description: frequency register 2 register address: 0dh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name freq[15:8] default 0 0 0 0 0 0 0 0 bits 7 to 0: current dpll frequency (freq[15:8]). see the freq1 register description.
________________________________________________________________________________________ ds 3104-se 64 register name: valsr1 register description: input clock valid status register 1 register address: 0eh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ic8 ? ic6 ic5 ic4 ic3 ic2 ic1 default 0 0 0 0 0 0 0 0 bits 7 and 5 to 0: input clock valid status (ic8 and ic[6:1]). each of these real-time status bits is set to 1 when the corresponding input clock is valid. an input is valid if it has no active alarms (act = 0, lock = 0 in the corresponding isr register). see also the msr1 register and section 7.5 . 0 = invalid 1 = valid register name: valsr2 register description: input clock valid status register 2 register address: 0fh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? hordy ? ? ? ? ? ic9 default 0 0 0 0 0 0 0 0 bit 6: holdover frequency ready (hordy). this real-time status bit is set to 1 when the t0 dpll has a holdover value that has been averaged over the one-second holdover averag ing period. see the related latched status bit in msr4 and section 7.7.1.6 . bit 0: input clock valid status (ic9). this bit has the same behavior as the bits in valsr1 but for the ic9 clock.
________________________________________________________________________________________ ds 3104-se 65 register name: isr1 register description: input status register 1 register address: 10h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? act2 lock2 ? ? act1 lock1 default 0 0 1 0 0 0 1 0 bit 5: activity alarm for input clock 2 (act2). this real-time status bit is set to 1 when the leaky bucket accumulator for ic2 reaches the alarm threshold specified in the lbxu register (where ?x? in ?lbxu? is specified in the bucket field of icr1 ). an activity alarm clears the ic2 status bit in the valsr1 register, invalidating the ic2 clock. see section 7.5.2 . bit 4: phase lock alarm for input clock 2 (lock2). this status bit is set to 1 if ic2 is the selected reference and the t0 dpll cannot phase lock to ic2 within the duration specified in the phlkto register (default = 100 seconds). a phase lock alarm clears the ic2 status bit in valsr1 , invalidating the ic2 clock. if lkato = 1 in mcr3 then lock2 is automatically cleared after a timeout period of 128 seconds. lock2 is a read/write bit. system software can clear lock4 by writing 0 to it, but writing 1 is ignored. see section 7.7.1 . bit 1: activity alarm for input clock 1 (act1). this bit has the same behavior as the act2 bit but for the ic1 input clock. bit 0: phase lock alarm for input clock 1 (lock1). this bit has the same behavior as the lock2 bit but for the ic1 input clock. register name: isr2 register description: input status register 2 register address: 11h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? act4 lock4 ? ? act3 lock3 default 0 0 1 0 0 0 1 0 bit 5: activity alarm for input clock 4 (act4). this real-time status bit is set to 1 when the leaky bucket accumulator for ic4 reaches the alarm threshold specified in the lbxu register (where ?x? in ?lbxu? is specified in the bucket field of icr4 ). an activity alarm clears the ic4 status bit in the valsr1 register, invalidating the ic4 clock. see section 7.5.2 . bit 4: phase lock alarm for input clock 4 (lock4). this status bit is set to 1 if ic4 is the selected reference and the t0 dpll cannot phase lock to ic4 within the duration specified in the phlkto register (default = 100 seconds). a phase lock alarm clears the ic4 status bit in valsr1 , invalidating the ic4 clock. if lkato = 1 in mcr3 then lock4 is automatically cleared after a timeout period of 128 seconds. lock4 is a read/write bit. system software can clear lock4 by writing 0 to it, but writing 1 is ignored. see section 7.7.1 . bit 1: activity alarm for input clock 3 (act3). this bit has the same behavior as the act4 bit but for the ic3 input clock. bit 0: phase lock alarm for input clock 3 (lock3). this bit has the same behavior as the lock4 bit but for the ic3 input clock.
________________________________________________________________________________________ ds 3104-se 66 register name: isr3 register description: input status register 3 register address: 12h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? act6 lock6 ? ? act5 lock5 default 0 0 1 0 0 0 1 0 this register has the same behavior as the isr1 and isr2 registers, but for input clocks ic5 and ic6. register name: isr4 register description: input status register 4 register address: 13h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? act8 lock8 ? ? ? ? default 0 0 1 0 0 0 0 0 this register has the same behavior as the isr1 and isr2 registers, but for input clock ic8. register name: isr5 register description: input status register 5 register address: 14h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? ? ? act9 lock9 default 0 0 0 0 0 0 1 0 this register has the same behavior as the isr1 and isr2 registers, but for input clock ic9.
________________________________________________________________________________________ ds 3104-se 67 register name: msr4 register description: master status register 4 register address: 17h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? hordy mraa ? ? ? ? ? default 0 0 0 0 0 0 0 0 bit 6: holdover frequency ready (hordy). this latched status bit is set to 1 when the t0 dpll has a holdover value that has been averaged over the 1-second holdover averaging period. hordy is cleared when written with a 1. when hordy is set it can cause an interrupt request on the intreq pin if the hordy interrupt enable bit is set in the ier4 register. see section 7.7.1.6 . bit 5: multiregister access aborted (mraa). this latched status bit is set to 1 when a multibyte access (read or write) is interrupted by another access to the device. mraa is cleared when written with a 1. mraa cannot cause an interrupt to occur. see section 8.3 .
________________________________________________________________________________________ ds 3104-se 68 register name: ipr1 register description: input priority register 1 register address: 18h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name pri2[3:0] pri1[3:0] default (t0) 0 0 0 1 0 0 0 0 default (t4) 0 0 0 1 0 0 0 0 bits 7 to 4: priority for input clock 2 (pri2[3:0]). priority 0001 is highest; priority 1111 is lowest. when mcr11 :t4t0 = 0, pri2 configures ic2?s priority for the t0 dp ll. when t4t0 = 1, pri2 c onfigures ic2?s priority for the t4 path. see section 7.6.1 . 0000 = ic2 unavailable for selection. 0001?1111= ic2 relative priority bits 3 to 0: priority for input clock 1 (pri1[3:0]). priority 0001 is highest; priority 1111 is lowest. when mcr11 :t4t0 = 0, pri1 configures ic1?s priority for the t0 dp ll. when t4t0 = 1, pri1 c onfigures ic1?s priority for the t4 path. see section 7.6.1 . 0000 = ic1 unavailable for selection. 0001?1111= ic1 relative priority register name: ipr2 register description: input priority register 2 register address: 19h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name pri4[3:0] pri3[3:0] default (t0) 0 0 1 1 0 0 1 0 default (t4) 0 0 1 1 0 0 1 0 bits 7 to 4: priority for input clock 4 (pri4[3:0]). priority 0001 is highest; priority 1111 is lowest. when mcr11 :t4t0 = 0, pri4 configures ic4?s priority for the t0 dp ll. when t4t0 = 1, pri4 c onfigures ic4?s priority for the t4 path. see section 7.6.1 . 0000 = ic4 unavailable for selection 0001?1111= ic4 relative priority bits 3 to 0: priority for input clock 3 (pri3[3:0]). priority 0001 is highest; priority 1111 is lowest. when mcr11 :t4t0 = 0, pri3 configures ic3?s priority for the t0 dp ll. when t4t0 = 1, pri3 c onfigures ic3?s priority for the t4 path. see section 7.6.1 . 0000 = ic3 unavailable for selection 0001?1111= ic3 relative priority register name: ipr3 register description: input priority register 3 register address: 1ah bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name pri6[3:0] pri5[3:0] default (t0) 0 0 0 0 0 0 0 0 default (t4) 0 0 0 0 0 0 0 0 these registers have the same behavior as ipr2 but for input clocks ic5 and ic6.
________________________________________________________________________________________ ds 3104-se 69 register name: ipr4 register description: input priority register 4 register address: 1bh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name pri8[3:0] ? default (t0) 0 1 0 0 0 0 0 0 default (t4) 0 1 0 1 0 0 0 0 these registers have the same behavior as ipr2 but for input clock ic8. register name: ipr5 register description: input priority register 5 register address: 1ch bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? pri9[3:0] default (t0) 0 0 0 0 0 1 0 1 default (t4) 0 0 0 0 0 0 0 0 these registers have the same behavior as ipr2 but for input clock ic9.
________________________________________________________________________________________ ds 3104-se 70 register name: icr1, icr2, icr3, icr4, icr5, icr6, icr8, icr9 register description: input configuration register 1, 2, 3, 4, 5, 6, 8, 9 register address: 20h, 21h, 22h, 23h, 24h, 25h, 27h, 28h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name divn lock8k bucket[1:0] freq[3:0] default 0 0 0 0 see below note: these registers are identical in function. icrx is the control register for input clock icx. bit 7: divn mode (divn). when divn is set to 1 and lock8k = 0, the input clock is divided down by a programmable predivider. the resulting output clock is then passed to the dpll. all input clocks for which divn = 1 are divided by the factor specified in divn1 and divn2 . when divn = 1 and lock8k = 0 in an icr register, the freq field of that register must be set to the input frequency divided by the divide factor. when divn = 1 and lock8k = 1 in an icr register, the freq field of that register is decoded as the alternate frequencies. see sections 7.4.2.2 and 7.4.2.4 . 0 = disabled 1 = enabled bit 6: lock8k mode (lock8k). when lock8k is set to 1 and divn = 0, the input clock is divided down by a preset predivider. the resulting output clock, which is always 8khz, is then passed to the dpll. lock8k is ignored when divn = 0 and freq[3:0] = 1001 (2khz) or 1010 (4khz). in addition, lock8k mode cannot be used with 5mhz input clocks. when divn = 1 and lock8k = 1 in an icr register, the freq field of that register is decoded as the alternate frequencies. see sections 7.4.2.2 and 7.4.2.3 0 = disabled 1 = enabled bits 5 to 4: leaky bucket configuration (bucket[1:0]). each input clock has leaky bucket accumulator logic in its activity monitor. the lbxy registers at addresses 50h to 5fh specify four different leaky bucket configurations. any of the four configurations can be s pecified for the input clock. see section 7.5.2 . 00 = leaky bucket configuration 0 01 = leaky bucket configuration 1 10 = leaky bucket configuration 2 11 = leaky bucket configuration 3 bits 3 to 0: input clo ck frequency (freq[3:0]). when divn = 0 and lock8k = 0 (standard direct-lock mode), this field specifies the input clock?s nominal frequency for direct-lock operation. when divn = 0 and lock8k = 1 (lock8k mode) this field specifies the input clock?s no minal frequency for lock8k operation. when divn = 1 and lock8k = 0 (divn mode), this field specifies the frequen cy after the divn divider (i.e., input frequency divided by divn + 1). when divn = 1 and lock8k = 1 (alternate direct-lock frequencies), this field specifies the input clock?s nominal frequency for direct-lock operation. divn = 0 or lock8k = 0: (standard direct -lock mode, lock8k mode, or divn mode) 0000 = 8khz 0001 = 1544 or 2048khz (as determined by sonsdh bit in the mcr3 register) 0010 = 6.48mhz 0011 = 19.44mhz 0100 = 25.92mhz 0101 = 38.88mhz 0110 = 51.84mhz 0111 = 77.76mhz 1000 = 155.52mhz (only valid for lvds inputs) 1001 = 2khz 1010 = 4khz 1011 = 6312khz 1100 = 5mhz 1101 = 31.25 mhz (not a multiple of 8 khz and therefore not valid for lock8k mode) 1110 to 1111 = undefined
________________________________________________________________________________________ ds 3104-se 71 divn = 1 and lock8k = 1: (alter nate direct-lock frequency decode) 0000 = 10mhz (internally divided down to 5mhz) 0001 = 25mhz (internally divided down to 5mhz) 0010 = 62.5mhz (internally down to 31.25mhz) 0011 = 125mhz (internally down to 31.25mhz) 0100 = 156.25mhz (differential inputs only. internally divided down to 31.25mhz) 0101 to 1111 = undefined freq[3:0] default values: icr1 ? icr4:0000b icr5 ? icr9:0011b register name: valcr1 register description: input clock valid control register 1 register address: 30h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ic8 ? ic6 ic5 ic4 ic3 ic2 ic1 default 1 0 1 1 1 1 1 1 bits 7 and 5 to 0: input clock valid control (ic8 and ic[6:1]). these control bits can be used to force input clocks to be considered invalid. if a clock is invalidated by o ne of these control bits it will not appear in the priority table in the ptab1 and ptab2 registers, even if the clock is otherwise valid. these bits are useful when system software needs to force clocks to be invalid in response to oam commands. note that setting a valcr bit low has no effect on the corresponding bit in the valsr registers. see sections 7.6.2 . 0 = force invalid 1 = don?t force invalid; determine validity normally register name: valcr2 register description: input clock valid control register 2 register address: 31h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? ? ? ? ic9 default 0 0 0 0 0 0 0 1 bit 0: input clock valid control (ic9). this bit has the same behavior as the bits in valcr1 but for the ic9 input clock.
________________________________________________________________________________________ ds 3104-se 72 register name: mcr1 register description: master configuration register 1 register address: 32h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name rst ? fren lockpin ? t0state[2:0] default 0 0 1 0 0 0 0 0 bit 7: device reset (rst). when this bit is high the entire device is held in reset, and all register fields, except the rst bit itself, are reset to their default states. when rst is active, the register fields with pin-programmed defaults do not latch their values from the corresponding input pins. instead these fields are reset to the default values that were latched from the pins when the rst pin was last active. see section 7.11 . 0 = normal operation 1 = reset bit 5: frequency range detect enable (fren). when this bit is high the frequency of each input clock is measured and used to quickly declare the input inactive. 0 = frequency range detect disabled 1 = frequency range detect enabled bit 4: t0 dpll lock pin enable (lockpin). when this bit is high the lock pin indicates when the t0 dpll state machine is in the lock state ( opstate .t0state = 100). 0 = lock pin is not driven 1 = lock pin is driven high when the t0 dpll is in the lock state bits 2 to 0: t0 dpll state control (t0state[2:0]). this field allows the t0 dpll state machine to be forced to a specified state. the state machine will remain in the fo rced state, and therefore cannot react to alarms and other events, as long as t0state is not equal to 000. see section 7.7.1 . 000 = automatic (normal state machine operation) 001 = free-run 010 = holdover 011 = {unused value} 100 = locked 101 = prelocked 2 110 = prelocked 111 = loss-of-lock
________________________________________________________________________________________ ds 3104-se 73 register name: mcr2 register description: master configuration register 2 register address: 33h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? t0force[3:0] default 0 0 0 0 1 1 1 1 bits 3 to 0: t0 dpll force selected reference (t0force[3:0]). this field provides a way to force a specified input clock to be the selected reference for the t0 dpll. inte rnally this is accomplished by forcing the clock to have the highest priority (as specified in ptab1 :ref1). in revertive mode ( mcr3 :revert = 1) the forced clock automatically becomes the select ed reference (as specified in ptab1 :selref) as well. in nonrevertive mode the forced clock only becomes the selected reference when t he existing selected reference is invalidated or made unavailable for selection. when a reference is forced, the activity monitor for t hat input and the t0 dpll?s loss-of-lock timeout logic all continue to operate and affect the relevant isr , valsr and msr register bits. however, when the reference is declared invalid the t0 dpll is not allowed to switch to another input clock. the t0 dpll continues to respond to the fast activity monitor, transitioning to mini-holdover in response to short-term events and to full holdover in response to longer events. see section 7.6.3 . 0000 = automatic source selection (normal operation) 0001 = force to ic1 0010 = force to ic2 0011 = force to ic3 0100 = force to ic4 0101 = force to ic5 0110 = force to ic6 0111 = {unused value} 1000 = force to ic8 1001 = force to ic9 1010 to 1110 = {unused values} 1111 = automatic source selection (normal operation)
________________________________________________________________________________________ ds 3104-se 74 register name: mcr3 register description: master configuration register 3 register address: 34h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name aefsen lkato xoedge fr unho efsen sonsdh ? revert default 1 1 0 0 1 see below 1 0 bit 7: auto external frame sync enable (aefsen). this bit has two modes depending on the source field of fscr3 . see section 7.9 . source! = 11xx: 0 = efsen bit (bit 3 below) enables and disables the external frame sync on the syncn pin 1 = the external frame sync is enabled when efsen = 1 and the t0 dpll is locked to the input clock specified in the source field of fscr3 . source = 11xx: 0 = external frame sync enabled according to efsen bit. 1 = when the selected reference changes the efsen bit clears and the external frame sync is disabled. (efsen bit must be set to enable it again.) bit 6: phase lock alarm timeout (lkato). this bit controls how phase alarms on input clocks can be terminated. phase alarms are indicated by the lock bits in isr registers. 0 = phase alarms on input clocks can only be cancelled by software. 1 = phase alarms are automatically cancelled after a timeout period of 128 seconds. bit 5: local oscillator edge (xoedge). this bit specifies the si gnificant clock e dge of the local oscillator clock signal on the refclk input pin. the faster edge sh ould be selected for best jitter performance. see section 7.3 . 0 = rising edge 1 = falling edge bit 4: free-run holdover (frunho). when this bit is set to 1 the t0 dpll holdover frequency is set to 0ppm so the output frequency accuracy is set by the external oscillator accuracy. th is effects both mini-holdover and the holdover state. 0 = digital holdover 1 = free-run holdover, 0ppm bit 3: external frame sync enable (efsen). when this bit is set to 1 the t0 dpll looks for a frame sync pulse on the syncn pin(s). when fscr3 .source = 11xx the function of this bit can be modified according to the setting of the aefsen bit. see the aefsen bit descr iption above for more information. see section 7.9 . 0 = disable external frame sync; ignore syncn pin(s) 1 = enable external frame sync on syncn pin(s) bit 2: sonet or sdh frequencies (sonsdh). this bit specifies the clock rate for input clocks with freq = 0001 in the icr registers (20h to 28h). during reset the default value of this bit is latched from the sonsdh pin. see section 7.4.2 . 0 = 2048khz 1 = 1544khz bit 0: revertive mode (revert). this bit configures the t0 dpll for revertive or nonrevertive operation. (the t4 dpll is always revertive). in revertiv e mode, if an input clock with a higher priority than the selected reference becomes valid, the higher priority reference immediately becomes the selected reference. in nonrevertive mode the higher priority reference does not immediately become the selected reference but does become the highest-priority reference in the priority table (ref1 field in the ptab1 register). see section 7.6.2 .
________________________________________________________________________________________ ds 3104-se 75 register name: mcr4 register description: master configuration register 4 register address: 35h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name lkt4t0 ? ? ? t4force[3:0] default 0 0 0 0 0 0 0 0 bit 7: lock t4 to t0 (lkt4t0). when this bit is set to 1 (and t0cr1 :t4apt0 = 0) all output clocks are generated from the t0 dpll, and the t4cr1 :t4freq field selects the frequency of the t4 apll. see section 7.8.2.2 . when lkt4t0 = 0, the t4 apll can be locked to either t he t4 dpll or the t0 dpll depending on the setting of t0cr1 :t4apt0. 0 = t4 apll can lock to either t4 or the t0 dpll 1 = t4 apll always locked to the t0 dpll bits 3 to 0: t4 dpl force selected reference (t4force[3:0]). this field provides a way to force a specified input clock to be the selected reference for the t4 dpll. inte rnally this is accomplished by forcing the clock to have the highest priority (as specified in ptab1 :ref1). since the t4 dpll always operates in revertive mode, the forced clock automatically becomes t he selected reference (as specified in ptab1 :selref) as well. when a reference is forced, the activity monitor for t hat input continues to operate and affect the relevant isr , valsr and msr register bits. however, when the reference is declared invalid, the t4 dpll is not allowed to switch to another input clock. see section 7.6.3 . 0000 = automatic source selection (normal operation) 0001 = force to ic1 0010 = force to ic2 0011 = force to ic3 0100 = force to ic4 0101 = force to ic5 0110 = force to ic6 0111 = {unused value} 1000 = force to ic8 1001 = force to ic9 1010 to 1110 = {unused value} 1111 = automatic source selection (normal operation)
________________________________________________________________________________________ ds 3104-se 76 register name: mcr5 register description: master configuration register 5 register address: 36h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name rsv4 rsv3 rsv2 rsv1 ic2sf ic1sf ic6sf ic5sf default 0 0 0 0 0 0 0 0 bits 7 to 4: reserved bit 4 to 1 (rsv[4:1]). these bits are reserved for future use, and can be written to and read back. bit 3: input clock 2 signal format (ic2sf). for backward compatibility this bit can be written to and read back, but it does not affect the ic2pos/neg inputs pins. see section 7.4.1 . bit 2: input clock 1 signal format (ic1sf). for backward compatibility this bit can be written to and read back, but it does not affect the ic1pos/neg inputs pins. see section 7.4.1 . bit 1: input clock 6 signal format (ic6sf). for backward compatibility this bit can be written to and read back, but it does not affect the ic6pos/neg inputs pins. see section 7.4.1 . bit 0: input clock 5 signal format (ic5sf). for backward compatibility this bit can be written to and read back, but it does not affect the ic5pos/neg inputs pins. see section 7.4.1 .
________________________________________________________________________________________ ds 3104-se 77 register name: ocr6 register description: output configuration register 6 register address: 37h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? oc5en oc4en oc5ben oc4ben oc3ben oc2ben oc1ben default 0 1 1 0 0 0 0 0 bit 6: oc5 output enable (oc5en). enables the oc5 output pin. 0 = output clock pin disabled, drives low. 1 = output clock pin controlled by ocr3 .ofreq5. bit 5: oc4 output enable (oc4en). enables the oc4 output pin. 0 = output clock pin disabled, drives low. 1 = output clock pin controlled by ocr2 .ofreq4. bit 4: oc5b output enable (oc5ben). enables the oc5b output pin. 0 = output clock pin disabled, drives low. 1 = output clock pin controlled by ocr3 .ofreq5. bit 3: oc4b output enable (oc4ben). enables the oc4b output pin. 0 = output clock pin disabled, drives low. 1 = output clock pin controlled by ocr2 .ofreq4. bit 2: oc3b output enable (oc3ben). selects gpio3 or oc3b function for the oc3b/gpio3pin. 0 = gpio3 functionality . 1 = output clock pin controlled by ocr2 .ofreq3. bit 1: oc2b output enable (oc2ben). selects gpio2 or oc2b function for the oc2b/gpio2pin. 0 = gpio2 functionality . 1 = output clock pin controlled by ocr1 .ofreq2. bit 0: oc1b output enable (oc1ben). selects gpio1 or oc1b function for the oc1b/gpio1pin. 0 = gpio1 functionality . 1 = output clock pin controlled by ocr1 .ofreq1.
________________________________________________________________________________________ ds 3104-se 78 register name: mcr6 register description: master configuration register 6 register address: 38h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name dig2af dig2ss dig1ss ? ? ? ? ? default 0 see below see below 1 1 1 1 1 bit 7: digital alternate frequency (dig2af). selects alternative frequencies. 0 = digital2 nxe1 or nxds1 frequency specified by dig2ss and mcr7 :dig2f. 1 = digital2 6.312mhz, 10mhz, or nx19.44mhz frequency specified by dig2ss and mcr7 :dig2f. bit 6: digital2 sonet or sdh frequencies (dig2ss). this bit specifies whether the clock rates generated by the digital2 clock synthesizer are mult iples of 1.544mhz (sonet-compatible ) or multiples of 2.048mhz (sdh- compatible) or alternate frequencies. the specific multiple is set in the dig2f field of the mcr7 register. when rst = 0 the default value of this bit is latched from the sonsdh pin. dig2af = 0: 0 = multiples of 2048khz 1 = multiples of 1544khz dig2af = 1: 6.312mhz, 10 mhz or nx19.44mhz bit 5: digital1 sonet or sdh frequencies (dig1ss). this bit specifies whether the clock rates generated by the digital1 clock synthesizer are multiples of 1544khz (sonet compatible) or multiples of 2048khz (sdh compatible). the specific multiple is set in the dig1f field of the mcr7 register. when rst = 0 the default value of this bit is latched from the sonsdh pin. 0 = multiples of 2048khz 1 = multiples of 1544khz
________________________________________________________________________________________ ds 3104-se 79 register name: mcr7 register description: master configuration register 7 register address: 39h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name dig2f[1:0] dig1f[1: 0] ? ? dig2src dig1src default 0 0 0 0 1 0 0 0 bits 7 to 6: digital2 frequency (dig2f[1:0]). this field, mcr6 :dig2ss and mcr6 :dig2af configure the frequency of the digital2 clock synthesizer. dig2af = 0 dig2af = 1 dig2ss = 1 dig2ss = 0 dig2ss = 1 dig2ss = 0 00 = 1544khz 00 = 2048khz 00 = 19.44mhz 00 = 6.312mhz 01 = 3088khz 01 = 4096khz 01 = 38.88mhz 01 = undefined 10 = 6176khz 10 = 8192khz 10 = undefined 10 = 10mhz 11 = 1235 khz 11 = 16384khz 11 = undefined 11 = undefined bits 5 to 4: digital1 frequency (dig1f[1:0]). this field and mcr6 :dig1ss configure the frequency of the digital1 clock synthesizer. dig1ss = 1 dig1ss = 0 00 = 1544khz 00 = 2048khz 01 = 3088khz 01 = 4096khz 10 = 6176khz 10 = 8192khz 11 = 12352khz 11 = 16384khz bit 1: digital2 source (dig2src). this bit selects which dpll the digital 2 dfs is connected to. when mcr4 :lkt4t0 = 1 it is always connected to the t0 dpll. 0 = the t0 dpll 1 = the t4 dpll bit 0: digital1 source (dig1src). this bit selects which dpll the digital 1 dfs is connected to. when mcr4 :lkt4t0 = 1 it is always connected to the t0 dpll. 0 = the t0 dpll 1 = the t4 dpll
________________________________________________________________________________________ ds 3104-se 80 register name: mcr8 register description: master configuration register 8 register address: 3ah bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name oc5sf[1:0] oc4sf[1:0] oc7sf[1:0] oc6sf[1:0] default 0 0 0 0 0 0 0 0 bits 7 to 6: output clock 5 signal format (oc5sf[1:0]). see section 7.8.1 . 00 = output disabled (default) 01 = 3v lvpecl level compatible 10 = 3v lvds compatible 11 = 3v lvds compatible bits 5 to 4: output clock 4 signal format (oc4sf[1:0]). see section 7.8.1 . 00 = output disabled (default) 01 = 3v lvpecl level compatible 10 = 3v lvds compatible 11 = 3v lvds compatible bits 3 to 2: output clock 7 signal format (oc7sf[1:0]). see section 7.8.1 . 00 = output disabled (default) 01 = 3v lvpecl level compatible 10 = 3v lvds compatible 11 = 3v lvds compatible bits 1 to 0: output clock 6 signal format (oc6sf[1:0]). see section 7.8.1 . 00 = output disabled (default) 01 = 3v lvpecl level compatible 10 = 3v lvds compatible 11 = 3v lvds compatible register name: mcr9 register description: master configuration register 9 register address: 3bh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name autobw ? ? ? limint ? ? ? default 1 1 1 1 1 0 1 1 bit 7: automatic bandwidth selection (autobw). see section 7.7.3 . 0 = always selects locked bandwidth from the t0lbw register 1 = automatically selects either locked bandwidth ( t0lbw register) or acquisition bandwidth ( t0abw register) as appropriate bit 3: limit integral path (limint). when this bit is set to 1, the t0 dpll?s integral path is limited (i.e., frozen) when the dpll reaches minimum or maximum fr equency, as set by the hardlim field in dlimit1 and dlimit2 . when the integral path is frozen, the current dpll frequency in registers freq1 , freq2 and freq3 is also frozen. setting limint = 1 minimizes overshoot when the dpll is pulling in. see section 7.7.3 . 0 = do not freeze integral path at min/max frequency 1 = freeze integral path at min/max frequency
________________________________________________________________________________________ ds 3104-se 81 register name: mclk1 register description: master clock frequency adjustment register 1 register address: 3ch bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name mclkfreq[7:0] default 1 0 0 1 1 0 0 1 note: the mclk1 and mclk2 registers must be read consec utively and written consecutively. see section 8.3 . bits 7 to 0: master clock freque ncy adjustment (mclkfreq[7:0]). the full 16-bit mclkfreq[15:0] field spans this register and mclk2. mclkfreq is an unsigned integer that adjusts the frequency of the internal 204.8mhz master clock with respect to the frequency of t he local oscillator clock on the refclk pin by up to +514ppm and -771ppm. the master clock adjustment has the effe ct of speeding up the master clock with a positive adjustment and slowing it down with a negative adjustment. for example, if the oscillator connected to refclk has an offset of +1ppm the adjustment should be -1ppm to correct the offset. the formulas below translate adjustments to register valu es and vice versa. the def ault register value of 39,321 corresponds to 0ppm. see section 7.3 . mclkfreq[15:0] = adjustment_in_ppm / 0.0196229 + 39,321 adjustment_in_ppm = ( mclkfreq[15:0] ? 39,321 ) x 0.0196229 register name: mclk2 register description: master clock frequency adjustment register 2 register address: 3dh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name mlckfreq[15:8] default 1 0 0 1 1 0 0 1 bits 7 to 0: master clock frequency adjustment (mclkfreq[15:8]). see the mclk1 register description. register name: hocr3 register description: holdover configuration register 3 register address: 40h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name avg ? ? ? ? default 1 0 0 0 1 0 0 0 note: see section 8.3 for important information about writing and reading this register. bit 7: averaging (avg). when this bit is set to 1 the t0 dpll uses the averaged frequency value during holdover mode. when frunho = 1 in the mcr3 register, this bit is ignored. see section 7.7.1.6 . 0 = not averaged frequency; holdover frequency is eit her free-run (frunho = 1) or instantaneously frozen 1 = averaged frequency over the last 1 second while locked to the input
________________________________________________________________________________________ ds 3104-se 82 register name: dlimit1 register description: dpll frequency limit register 1 register address: 41h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name hardlim[7:0] default 0 1 1 1 0 1 1 0 the dlimit1 and dlimit2 registers must be read consec utively and written consecutively. see section 8.3 . bits 7 to 0: dpll hard frequency limit (hardlim[7:0]). the full 10-bit hardlim[9:0] field spans this register and dlimit2 . hardlim is an unsigned integer that specifies the ha rd frequency limit or pull-in/hold-in range of the t0 dpll. when frequency limit detection is enabled by setting fllol = 1 in the dlimit3 register, if the dpll frequency exceeds the hard limit the dpll declares lo ss-of-lock. the hard frequency limit in ppm is hardlim[9:0] x 0.0782. the def ault value is normally 9.2ppm. if external reference switching mode is enabled during reset (see section 7.6.5 ), the default value is configured to 79.794ppm (3ffh). see section 7.7.6 . register name: dlimit2 register description: dpll frequency limit register 1 register address: 42h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? ? ? hardlim[9:8] default 0 0 0 0 0 0 0 0 bits 1 to 0: dpll hard frequency limit (hardlim[9:8]). see the dlimit1 register description.
________________________________________________________________________________________ ds 3104-se 83 register name: ier1 register description: interrupt enable register 1 register address: 43h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ic8 ? ic6 ic5 ic4 ic3 ic2 ic1 default 0 0 0 0 0 0 0 0 bits 7 and 5 to 0: interrupt enable for input clock status change (ic8 and ic[6:1]). each of these bits is an interrupt enable control for the corresponding bit in the msr1 register. 0 = mask the interrupt 1 = enable the interrupt register name: ier2 register description: interrupt enable register 2 register address: 44h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name state srfail ? ? ? ? ? ic9 default 0 0 0 0 0 0 0 0 bit 7: interrupt enable for t0 dpll state change (state). this bit is an interrupt enable for the state bit in the msr2 register. 0 = mask the interrupt 1 = enable the interrupt bit 6: interrupt enable for sel ected reference failed (srfail). this bit is an interrupt enable for the srfail bit in the msr2 register. 0 = mask the interrupt 1 = enable the interrupt bit 0: interrupt enable for input clock status change (ic9). this bit is an interrupt enable control for the ic9 bit in the msr2 register. 0 = mask the interrupt 1 = enable the interrupt
________________________________________________________________________________________ ds 3104-se 84 register name: ier3 register description: interrupt enable register 3 register address: 45h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name fsmon t4lock ? t4noin ? ? ? ? default 0 0 0 0 0 0 0 0 bit 7: interrupt enable for frame sync input monitor alarm (fsmon). this bit is an interrupt enable for the fsmon bit in the msr3 register. 0 = mask the interrupt 1 = enable the interrupt bit 6: interrupt enable for the t4 dpll lock status change (t4lock). this bit is an interrupt enable for the t4lock bit in the msr3 register. 0 = mask the interrupt 1 = enable the interrupt bit 4: interrupt enable for t4 no valid inputs alarm (t4noin). this bit is an interrupt enable for the t4noin bit in the msr3 register. 0 = mask the interrupt 1 = enable the interrupt
________________________________________________________________________________________ ds 3104-se 85 register name: divn1 register description: divn register 1 register address: 46h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name divn[7:0] default 1 1 1 1 1 1 1 1 note: the divn1 and divn2 registers must be read consec utively and written consecutively. see section 8.3 . bits 7 to 0: divn factor (divn[7:0]). the full 16-bit divn[15:0] field spans this register and divn2 . this field contains the integer value used to divide the frequency of input clocks that are configured for divn mode. the frequency is divided by divn[15:0] + 1. see section 7.4.2.4 . register name: divn2 register description: divn register 2 register address: 47h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name divn[15:8] default 0 0 1 1 1 1 1 1 bits 7 to 0: divn factor (divn[15:8]). see the divn1 register description.
________________________________________________________________________________________ ds 3104-se 86 register name: mcr10 register description: master configuration register 10 register address: 48h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? srfpin ufsw extsw pbofrz pboen ? ? default 1 0 0 see below 0 1 0 0 bit 6: srfail pin enable (srfpin). when this bit is set to 1, the srfail pin is enabled. when enabled the srfail pin follows the state of the srfail status bit in the msr2 register. this gives the system a very fast indication of the failure of the current reference. see section 7.5.3 . 0 = srfail pin disabled (not driven) 1 = srfail pin enabled bit 5: ultra-fast switching mode (ufsw). see section 7.6.4 . 0 = disabled 1 = enabled. the current reference source is disqualified after less than three missing clock cycles. bit 4: external reference switching mode (extsw). this bit enables external reference switching mode. in this mode, if the srcsw pin is high the t0 dpll is forced to lock to input ic3 (i f the priority of ic3 is nonzero) or ic5 (if the priority of ic3 is zero) whether or not the selected input has a valid reference signal. if the srcsw pin is low the device is forced to lock to input ic4 (i f the priority of ic4 is nonzero) or ic6 (if the priority of ic4 is zero) whether or not the selected input has a valid reference signal. during reset the default value of this bit is latched from the srcsw pin. this mode only controls the t0 dp ll. the t4 dpll is not affected. see section 7.6.5 . 0 = normal operation 1 = external switching mode bit 3: phase build-out freeze (pbofrz). this bit freezes the current input -output phase relationship and does not allow further phase build-out events to occur. this bit affects phase build-out in response to reference switching (section 7.7.7.1 ). 0 = not frozen 1 = frozen bit 2: phase build-out enable (pboen). when this bit is set to 1 a phase build-out event occurs every time the t0 dpll changes to a new reference, including exiting the holdover and free-run states. when this bit is set to 0, the t0 dpll locks to the new source with ze ro degrees of phase difference. see section 7.7.7 . register name: mcr11 register description: master configuration register 11 register address: 4bh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? t4t0 ? ? ? ? default 0 0 0 0 0 0 0 0 bit 4: t4 or t0 path select (t4t0). this bit specifies which path is being ac cessed when reads or writes are made to the following registers: ptab1 , ptab2 , freq1 , freq2 , freq3 , ipr1 , ipr2 , ipr3 , ipr4 , ipr5 , phase1 , and phase2 . 0 = t0 path 1 = t4 path
________________________________________________________________________________________ ds 3104-se 87 register name: dlimit3 register description: dpll frequency limit register 3 register address: 4dh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name fllol softlim[6:0] default 1 0 0 0 1 1 1 0 bit 7: frequency limit loss of lock (fllol). when this bit is set to 1, the t0 dpll and the t4 dpll internally declare loss-of-lock when their hard limits are reach ed. the t0 dpll hard frequency limit is set in the hardlim[9:0] field in the dlimit1 and dlimit2 registers. the t4 dpll hard frequency limit is fixed at 80ppm. see section 7.7.6 . 0 = dpll declares loss-of-lock normally 1 = dpll also declares loss-of-lock when the hard frequency limit is reached bits 6 to 0: dpll soft frequency limit (softlim[6:0]). this field is an unsigned integer that specifies the soft frequency limit for the t0 dpll and the t4 dpll. the soft lim it is only used for monitoring; exceeding this limit does not cause loss-of-lock . the limit in ppm is softlim[6:0] x 0.628. the default value is 8.79ppm. when the t0 dpll frequency reaches the soft limit the t0soft status bit is set in the opstate register. when the t4 dpll frequency reaches the soft limit the t4soft status bit is set in opstate . see section 7.7.6 . register name: ier4 register description: interrupt enable register 4 register address: 4eh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? hordy ? ? ? ? ? ? default 0 0 0 0 0 0 0 0 bit 6: interrupt enable for holdover frequency ready (hordy). this bit is an interrupt enable for the hordy bit in the msr4 register. 0 = mask the interrupt 1 = enable the interrupt
________________________________________________________________________________________ ds 3104-se 88 register name: ocr5 register description: output configuration register 1 register address: 4fh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? aof7 aof6 aof5 aof4 aof3 aof2 aof1 default 0 0 0 0 0 0 0 0 bit 6: alternate output frequency mode select 7 (aof7). this bit controls the decoding of the ocr4 .ofreq7 field for the oc7 pin. 0 = standard decodes 1 = alternate decodes bit 5: alternate output frequency mode select 6 (aof6). this bit controls the decoding of the ocr3 .ofreq6 field for the oc6 pin. 0 = standard decodes 1 = alternate decodes bit 4: alternate output frequency mode select 5 (aof5). this bit controls the decoding of the ocr3 .ofreq5 field for the oc5 pin. 0 = standard decodes 1 = alternate decodes bit 3: alternate output frequency mode select 4 (aof4). this bit controls the decoding of the ocr2 .ofreq4 field for the oc4 pin. 0 = standard decodes 1 = alternate decodes bit 2: alternate output frequency mode select 3 (aof3). this bit controls the decoding of the ocr2 .ofreq3 field for the oc3 pin. 0 = standard decodes 1 = alternate decodes bit 1: alternate output frequency mode select 2 (aof2). this bit controls the decoding of the ocr1 .ofreq2 field for the oc2 pin. 0 = standard decodes 1 = alternate decodes bit 0: alternate output frequency mode select 1 (aof1). this bit controls the decoding of the ocr1 .ofreq1 field for the oc1 pin. 0 = standard decodes 1 = alternate decodes
________________________________________________________________________________________ ds 3104-se 89 register name: lb0u register description: leaky bucket 0 upper threshold register register address: 50h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name lb0u[7:0] default 0 0 0 0 0 1 1 0 bits 7 to 0: leaky bucket 0 upper threshold (lb0u[7:0]). when the leaky bucket accumulator is equal to the value stored in this field, the activity monitor declares an activity alarm by setting the input clock?s act bit in the appropriate isr register. registers lb0u , lb0l , lb0s and lb0d together specify leaky bucket configuration 0. see section 7.5.2 . register name: lb0l register description: leaky bucket 0 lower threshold register register address: 51h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name lb0l[7:0] default 0 0 0 0 0 1 0 0 bits 7 to 0: leaky bucket 0 lower threshold (lb0l[7:0]). when the leaky bucket accumulator is equal to the value stored in this field, the activity monitoring logic clears the activity alarm (if previously declared) by clearing the input clock?s act bit in the appropriate isr register. registers lb0u , lb0l , lb0s , and lb0d together specify leaky bucket configuration 0. see section 7.5.2 . register name: lb0s register description: leaky bucket 0 size register register address: 52h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name lb0s[7:0] default 0 0 0 0 1 0 0 0 bits 7 to 0: leaky bucket 0 size (lb0s[7:0]). this field specifies the maximum value of the leaky bucket. the accumulator cannot increment past this value. registers lb0u , lb0l , lb0s , and lb0d together specify leaky bucket configuration 0. see section 7.5.2 . register name: lb0d register description: leaky bucket 0 decay rate register register address: 53h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? ? ? lb0d[1:0] default 0 0 0 0 0 0 0 1 bits 1 to 0: leaky bucket 0 decay rate (lb0d[1:0]). this field specifies the decay or ?leak? rate of the leaky bucket accumulator. for each period of 1, 2, 4, or 8 128ms intervals in which no irregularities are detected on the input clock, the accumulator decrements by 1. registers lb0u , lb0l , lb0s , and lb0d together specify leaky bucket configuration 0. see section 7.5.2 . 00 = decrement every 128ms (8 units/second) 01 = decrement every 256ms (4 units/second) 10 = decrement every 512ms (2 units/second) 11 = decrement every 1024ms (1 unit/second)
________________________________________________________________________________________ ds 3104-se 90 register name: lb1u, lb2u, lb3u register description: leaky bucket 1/2/3 upper threshold register register address: 54h, 58h, 5ch bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name lbxu[7:0] default 0 0 0 0 0 1 1 0 bits 7 to 0: leaky bucket ?x? upper threshold (lbxu[7:0]). see the lb0u register description. registers lb1u , lb1l , lb1s , and lb1d together specify leaky bu cket configuration 1. registers lb2u , lb2l , lb2s , and lb2d together specify leaky bu cket configuration 2. registers lb3u , lb3l , lb3s , and lb3d together specify leaky bu cket configuration 3. register name: lb1l, lb2l, lb3l register description: leaky bucket 1/2/3 lower threshold register register address: 55h, 59h, 5dh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name lbxl[7:0] default 0 0 0 0 0 1 0 0 bits 7 to 0: leaky bucket ?x? lower threshold (lbxl[7:0]). see the lb0l register description. registers lb1u , lb1l , lb1s , and lb1d together specify leaky bu cket configuration 1. registers lb2u , lb2l , lb2s , and lb2d together specify leaky bu cket configuration 2. registers lb3u , lb3l , lb3s , and lb3d together specify leaky bu cket configuration 3. register name: lb1s, lb2s, lb3s register description: leaky bucket 1/2/3 size register register address: 56h, 5ah, 5eh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name lbxs[7:0] default 0 0 0 0 1 0 0 0 bits 7 to 0: leaky bucket ?x? size (lbxs[7:0]). see the lb0s register description. registers lb1u , lb1l , lb1s , and lb1d together specify leaky bu cket configuration 1. registers lb2u , lb2l , lb2s , and lb2d together specify leaky bu cket configuration 2. registers lb3u , lb3l , lb3s , and lb3d together specify leaky bu cket configuration 3. register name: lb1d, lb2d, lb3d register description: leaky bucket 1/2/3 decay rate register register address: 57h, 5bh, 5fh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? ? ? lbxd[1:0] default 0 0 0 0 0 0 0 1 bits 1 to 0: leaky bucket ?x? decay rate (lbxd[1:0]). see the lb0d register description. registers lb1u , lb1l , lb1s , and lb1d together configure leaky bucket algorithm 1. registers lb2u , lb2l , lb2s , and lb2d together configure leaky bucket algorithm 2. registers lb3u , lb3l , lb3s , and lb3d together configure leaky bucket algorithm 3.
________________________________________________________________________________________ ds 3104-se 91 register name: ocr1 register description: output configuration register 1 register address: 60h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ofreq2[3:0] ofreq1[3:0] default 0 0 0 0 0 0 0 0 bits 7 to 4: output frequency of oc2 (ofreq2[3:0]). this field specifies the frequency of output clock oc2. the frequencies of the t0 apll and the t4 apll are configured in the t0cr1 and t4cr1 registers. the digital1 and digital2 frequencies are configured in the mcr7 register. see section 7.8.2.3 . the decode of this field is controlled by the value of the ocr5 .aof2 bit. aof2 = 0: (standard decodes) 0000 = output disabled (i.e., low) 0001 = 2khz 0010 = 8khz 0011 = digital2 (see table 7-8 ) 0100 = digital1 (see table 7-7 ) 0101 = t0 apll frequency divided by 48 0110 = t0 apll frequency divided by 16 0111 = t0 apll frequency divided by 12 1000 = t0 apll frequency divided by 8 1001 = t0 apll frequency divided by 6 1010 = t0 apll frequency divided by 4 1011 = t4 apll frequency divided by 64 1100 = t4 apll frequency divided by 48 1101 = t4 apll frequency divided by 16 1110 = t4 apll frequency divided by 8 1111 = t4 apll frequency divided by 4 aof2 = 1: (alternate decodes) 0000 = output disabled (i.e., low) 0001 = t0 apll frequency divided by 64 0010 = t4 apll frequency divided by 20 0011 = t4 apll frequency divided by 12 0100 = t4 apll frequency divided by 10 0101 = t4 apll frequency divided by 5 0110 = t4 apll frequency divided by 2 0111 = t4 selected reference (after dividing) 1000 to 1111 = undefined bits 3 to 0: output frequency of oc1 (ofreq1[3:0]). this field specifies the frequency of output clock oc1. the frequencies of the t0 apll and t4 apll are configured in the t0cr1 and t4cr1 registers. the digital1 and digital2 frequencies are configured in the mcr7 register. see section 7.8.2.3 . the decode of this field is controlled by the value of the ocr5 .aof1 bit. aof1 = 0: (standard decodes) 0000 = output disabled (i.e., low) 0001 = 2khz 0010 = 8khz 0011 = digital2 (see table 7-8 ) 0100 = digital1 (see table 7-7 ) 0101 = t0 apll frequency divided by 48 0110 = t0 apll frequency divided by 16 0111 = t0 apll frequency divided by 12 1000 = t0 apll frequency divided by 8 1001 = t0 apll frequency divided by 6 1010 = t0 apll frequency divided by 4
________________________________________________________________________________________ ds 3104-se 92 1011 = t4 apll frequency divided by 64 1100 = t4 apll frequency divided by 48 1101 = t4 apll frequency divided by 16 1110 = t4 apll frequency divided by 8 1111 = t4 apll frequency divided by 4 aof1 = 1: (alternate decodes) 0000 = output disabled (i.e., low) 0001 = t0 apll frequency divided by 64 0010 = t4 apll frequency divided by 20 0011 = t4 apll frequency divided by 12 0100 = t4 apll frequency divided by 10 0101 = t0 apll2 frequency divided by 10 0110 = t0 apll2 frequency divided by 5 0111 = t4 selected reference (after dividing) 1000 to 1111 = undefined
________________________________________________________________________________________ ds 3104-se 93 register name: ocr2 register description: output configuration register 2 register address: 61h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ofreq4[3:0] ofreq3[3:0] default 0 0 0 0 0 0 0 0 bits 7 to 4: output frequency of oc4 (ofreq4[3:0]). this field specifies the frequency of output clock oc4. the frequencies of the t0 apll and t4 apll are configured in the t0cr1 and t4cr1 registers. the digital1 and digital2 frequencies are configured in the mcr7 register. see section 7.8.2.3 . the decode of this field is controlled by the value of the ocr5 .aof4 bit. aof4 = 0: (standard decodes) 0000 = output disabled (i.e., low) 0001 = 2khz 0010 = 8khz 0011 = digital2 (see table 7-8 ) 0100 = digital1 (see table 7-7 ) 0101 = t0 apll frequency divided by 48 0110 = t0 apll frequency divided by 16 0111 = t0 apll frequency divided by 12 1000 = t0 apll frequency divided by 8 1001 = t0 apll frequency divided by 6 1010 = t0 apll frequency divided by 4 1011 = t4 apll frequency divided by 2 1100 = t4 apll frequency divided by 48 1101 = t4 apll frequency divided by 16 1110 = t4 apll frequency divided by 8 1111 = t4 apll frequency divided by 4 aof4 = 1: (alternate decodes) 0000 = output disabled (i.e., low) 0001 = t0 apll frequency divided by 2 0010 = t0 apll frequency 0011 = t4 apll frequency divided by 10 0100 = t0 apll2 frequency divided by 10 0101 = t0 apll2 frequency divided by 2 0110 = t0 apll2 frequency 0111 = t4 selected reference (after dividing) 1000 to 1111 = undefined bits 3 to 0: output frequency of oc3 (ofreq3[3:0]). this field specifies the frequency of output clock oc3. the frequencies of the t0 apll and t4 apll are configured in the t0cr1 and t4cr1 registers. the digital1 and digital2 frequencies are configured in the mcr7 register. see section 7.8.2.3 .the decode of this field is controlled by the value of the ocr5 .aof3 bit. aof3 = 0: (standard decodes) 0000 = output disabled (i.e., low) 0001 = 2khz 0010 = 8khz 0011 = digital2 (see table 7-8 ) 0100 = digital1 (see table 7-7 ) 0101 = t0 apll frequency divided by 48 0110 = t0 apll frequency divided by 16 0111 = t0 apll frequency divided by 12 1000 = t0 apll frequency divided by 8 1001 = t0 apll frequency divided by 6 1010 = t0 apll frequency divided by 4
________________________________________________________________________________________ ds 3104-se 94 1011 = t4 apll frequency divided by 64 1100 = t4 apll frequency divided by 48 1101 = t4 apll frequency divided by 16 1110 = t4 apll frequency divided by 8 1111 = t4 apll frequency divided by 4 aof3 = 1: (alternate decodes) 0000 = output disabled (i.e., low) 0001 = t0 apll frequency divided by 64 0010 = t4 apll frequency divided by 20 0011 = t4 apll frequency divided by 12 0100 = t4 apll frequency divided by 10 0101 = t4 apll frequency divided by 5 0110 = t4 apll frequency divided by 2 0111 = t4 selected reference (after dividing) 1000 to 1111 = undefined
________________________________________________________________________________________ ds 3104-se 95 register name: ocr3 register description: output configuration register 3 register address: 62h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ofreq6[3:0] ofreq5[3:0] default 0 0 0 0 0 0 0 0 bits 7 to 4: output frequency of oc6 (ofreq6[3:0]). this field specifies the freq uency of output clock output oc6. the frequencies of the t0 apll and t4 apll are configured in the t0cr1 and t4cr1 registers. the digital1 and digital2 frequencies are configured in the mcr7 register. see section 7.8.2.3 .the decode of this field is controlled by the value of the ocr5 .aof6 bit. aof6 = 0: (standard decodes) 0000 = output disabled (i.e., low) 0001 = 2khz 0010 = 8khz 0011 = t0 apll frequency divided by 2 0100 = digital1 (see table 7-7 ) 0101 = t0 apll frequency 0110 = t0 apll frequency divided by 16 0111 = t0 apll frequency divided by 12 1000 = t0 apll frequency divided by 8 1001 = t0 apll frequency divided by 6 1010 = t0 apll frequency divided by 4 1011 = t4 apll frequency divided by 64 1100 = t4 apll frequency divided by 48 1101 = t4 apll frequency divided by 16 1110 = t4 apll frequency divided by 8 1111 = t4 apll frequency divided by 4 aof6 = 1: (alternate decodes) 0000 = output disabled (i.e., low) 0001 = t4 apll frequency divided by 5 0010 = t4 apll frequency divided by 2 0011 = t4 apll frequency 0100 = t0 apll2 frequency divided by 5 0101 = t0 apll2 frequency divided by 2 0110 = t0 apll2 frequency 0111 = t4 selected reference (after dividing) 1000 to 1111 = undefined bits 3 to 0: output frequency of oc5 (ofreq5[3:0]). this field specifies the frequency of output clock oc5. the frequencies of the t0 apll and t4 apll are configured in the t0cr1 and t4cr1 registers. the digital1 and digital2 frequencies are configured in the mcr7 register. see section 7.8.2.3 . the decode of this field is controlled by the value of the ocr5 .aof5 bit. aof5 = 0: (standard decodes) 0000 = output disabled (i.e., low) 0001 = 2 khz 0010 = 8 khz 0011 = digital2 (see table 7-8 ) 0100 = digital1 (see table 7-7 ) 0101 = t0 apll frequency divided by 48 0110 = t0 apll frequency divided by 16 0111 = t0 apll frequency divided by 12 1000 = t0 apll frequency divided by 8 1001 = t0 apll frequency divided by 6 1010 = t0 apll frequency divided by 4
________________________________________________________________________________________ ds 3104-se 96 1011 = t4 apll frequency divided by 2 1100 = t4 apll frequency divided by 48 1101 = t4 apll frequency divided by 16 1110 = t4 apll frequency divided by 8 1111 = t4 apll frequency divided by 4 aof5 = 1: (alternate decodes) 0000 = output disabled (i.e., low) 0001 = t0 apll frequency divided by 2 0010 = t0 apll frequency 0011 = t4 apll frequency divided by 10 0100 = t0 apll2 frequency divided by 10 0101 = t0 apll2 frequency divided by 2 0110 = t0 apll2 frequency 0111 = t4 selected reference (after dividing) 1000 to 1111 = undefined
________________________________________________________________________________________ ds 3104-se 97 register name: ocr4 register description: output configuration register 4 register address: 63h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name mfsen fsen ? ? ofreq7[3:0] default 1 1 0 0 0 0 0 0 bit 7: mfsync enable (mfsen). this configuration bit enables the 2khz output on the mfsync pin. see section 7.8.2.4 . 0 = disabled, driven low 1 = enabled, output is 2khz bit 6: fsync enable (fsen). this configuration bit enables the 8khz output on the fsync pin. see section 7.8.2.4 . 0 = disabled, driven low 1 = enabled, output is 8khz bits 3 to 0: output frequency of oc7 (ofreq7[3:0]). this field specifies the freq uency of output clock output oc7. the frequencies of the t0 apll and t4 apll are configured in the t0cr1 and t4cr1 registers. the digital1 and digital2 frequencies are configured in the mcr7 register. see section 7.8.2.3 . the decode of this field is controlled by the value of the ocr5 .aof7 bit. aof7 = 0: (standard decodes) 0000 = output disabled (i.e., low) 0001 = 2khz 0010 = 8khz 0011 = digital2 (see table 7-8 ) 0100 = t0 apll frequency divided by 2 0101 = t0 apll frequency divided by 48 0110 = t0 apll frequency divided by 16 0111 = t0 apll frequency divided by 12 1000 = t0 apll frequency divided by 8 1001 = t0 apll frequency divided by 6 1010 = t0 apll frequency divided by 4 1011 = t4 apll frequency divided by 64 1100 = t4 apll frequency divided by 48 1101 = t4 apll frequency divided by 16 1110 = t4 apll frequency divided by 8 1111 = t4 apll frequency divided by 4 aof7 = 1: (alternate decodes) 0000 = output disabled (i.e., low) 0001 = t4 apll frequency divided by 5 0010 = t4 apll frequency divided by 2 0011 = t4 apll frequency 0100 = t0 apll2 frequency divided by 5 0101 = t0 apll2 frequency divided by 2 0110 = t0 apll2 frequency 0111 = t4 selected reference (after dividing) 1000 to 1111 = undefined
________________________________________________________________________________________ ds 3104-se 98 register name: t4cr1 register description: t4 dpll configuration register 1 register address: 64h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? t4freq[3:0] default 0 0 0 0 0 1 0 1 bits 3 to 0: t4 apll frequency (t4freq[3:0]). when t0cr1 :t4apt0 = 0, the t4 apll dfs is connected to the t4 dpll, and this field configures the t4 apll dfs frequency. the t4 apll dfs frequency affects the frequency of the t4 apll which in turn affects the ava ilable output frequencies on the output clock pins (see the ocr registers). see section 7.8.2 . t4freq[3:0] t4 apll dfs frequency t4 apll frequency (4 x t4 apll dfs) 0000 apll output disabled disabled, output is low 0001 77.76mhz 311.04mhz (4 x 77.76mhz) 0010 24.576mhz (12 x e1) 98.304mhz (48 x e1) 0011 32.768mhz (16 x e1) 131.072mhz (64 x e1) 0100 37.056mhz (24 x ds1) 148.224mhz (96 x ds1) 0101 24.704mhz (16 x ds1) 98.816mhz (64 x ds1) 0110 68.736mhz (2 x e3) 274.944mhz (8 x e3) 0111 44.736mhz (ds3) 178.944mhz (4 x ds3) 1000 25.248mhz (4 x 6312khz) 100.992mhz (16 x 6312khz) 1001 62.500mhz (gbe 16) 250.000mhz (gbe 4) 1010 30.720mhz (3 x 10.24) 122.880mhz (12 x 10.24) 1011 40.000mhz (4 x 10mhz) 160.000mhz (16 x 10mhz) 1100 26.000mhz (2 x 13mhz) 104.000mhz (8 x 13mhz) 1101?1111 {unused values} {unused values}
________________________________________________________________________________________ ds 3104-se 99 register name: t0cr1 register description: t0 dpll configuration register 1 register address: 65h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name t4mt0 t4apt0 t0ft4[2:0] t0freq[2:0] default 0 1 0 0 1 0 0 1 bit 7: t4 measure t0 phase (t4mt0). when this bit is set to 1 the t4 dpll goes to the free-run mode, and the t4 phase detector is configured to measure the phase diffe rence between the selected t0 dpll input clock and the selected the t4 dpll input clock. see section 7.7.10 . 0 = normal operation for the t4 path 1 = enable t4-measure-t0-phase mode bit 6: t4 apll source from t0 (t4apt0). when this bit is set to 0, the t4 apll dfs is connected to the t4 dpll, and t4cr1 :t4freq configures the t4 apll dfs frequency. the t4 apll dfs frequency affects the frequency of the t4 apll which in turn affects the ava ilable output frequencies on the output clock pins (see the ocr registers). when this bit is set to 1, the t4 apll df s is connected to the t0 dpll rather than the t4 dpll, and the frequency of the t4 apll dfs is configured by the t0cr1 :t0ft4[2:0] field below. see section 7.8.2 . 0 = t4 apll locks to t4 dpll 1 = t4 apll locks to t0 dpll bits 5 to 3: t0 frequency to t4 apll (t0ft4[2:0]). when the t4apt0 bit is set to 1, this field specifies the frequency of the t4 apll dfs. this frequency c an be different than the frequency specified by t0cr1 :t0freq. see section 7.8.2 . t0ft4 t4 apll dfs frequency t4 apll frequency (4 x t4 apll dfs) 000 = 24.576mhz (12 x e1) 98.304mhz (48 x e1) 001 = 62.500mhz (gbe 16) 250.000mhz (gbe 4) 010 = 32.768mhz (16 x e1) 131.072mhz (64 x e1) 011 = {unused value} {unused value} 100 = 37.056mhz (24 x ds1) 148.224mhz (96 x ds1) 101 = {unused value} {unused value} 110 = 24.704mhz (16 x ds1) 98.816mhz (64 x ds1) 111 = 25.248mhz (4 x 6312khz) 100.992mhz (16 x 6312khz) bits 2 to 0: t0 dpll output frequency (t0freq[2:0]). this field configures the t0 apll dfs frequency. the t0 apll dfs frequency affects the frequency of the t0 apll, which in turn affects the available output frequencies on the output clock pins (see the ocr registers). see section 7.8.2. t0freq t0 apll dfs frequency t0 apll frequency (4 x t0 apll dfs) 000 = 77.76mhz 311.04mhz (4 x 77.76mhz) 001 = 77.76mhz 311.04mhz (4 x 77.76mhz) 010 = 24.576mhz (12 x e1) 98.304mhz (48 x e1) 011 = 32.768mhz (16 x e1) 131.072mhz (64 x e1) 100 = 37.056mhz (24 x ds1) 148.224mhz (96 x ds1) 101 = 24.704mhz (16 x ds1) 98.816mhz (64 x ds1) 110 = 25.248mhz (4 x 6312khz) 100.992mhz (16 x 6312khz) 111 = 62.500mhz (gbe 16) 250.000mhz (gbe 4)
________________________________________________________________________________________ ds 3104-se 100 register name: t4bw register description: t4 bandwidth register register address: 66h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name 0 0 0 0 0 0 t4bw[1:0] default 0 0 0 0 0 0 0 0 bits 2 to 0: t4 dpll bandwidth (t4bw[2:0]). see section 7.7.3 . 000 = 18hz 001 = 35hz 010 = 70hz 011 = {unused value, undefined} register name: t0lbw register description: t0 dpll locked bandwidth register register address: 67h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? rsv1 t0lbw[3:0] default 0 0 0 0 1 1 0 1 bit 4: reserved bit 1 (rsv1). this bit is reserved for future use, it can be written to and read back. bits 3 to 0: t0 dpll locked bandwidth (t0lbw[3:0]). this field configures the bandwidth of the t0 dpll when locked to an input clock. when autobw = 0 in the mcr9 register, the t0lbw bandwidth is used for acquisition and for locked operation. when autobw = 1, t0abw bandwidth is used for acquisition while t0lbw bandwidth is used for locked operation. see section 7.7.3 . 1000 = 0.1hz 1001 = 0.3hz 1010 = 0.6hz 1011 = 1.2hz 1100 = 2.5hz 1101 = 4hz (default) 1110 = 8hz 1111 = 18hz 0000 = 35hz 0001 = 70hz 0010 = {unused values, undefined} 0011 = 18hz 0100 = 120hz 0101 = 250hz 0110 = 400hz 0111 = 18hz
________________________________________________________________________________________ ds 3104-se 101 register name: t0abw register description: t0 dpll acquisition bandwidth register register address: 69h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? rsv1 t0abw[3:0] default 0 0 0 0 1 1 1 1 bit 4: reserved bit 1 (rsv1). this bit is reserved for future use, it can be written to and read back. bits 3 to 0: t0 dpll acquisition bandwidth (t0abw[3:0]). this field configures the bandwidth of the t0 dpll when acquiring lock. when autobw = 0 in the mcr9 register, the t0lbw bandwidth is used for acquisition and for locked operation. when autobw = 1, t0abw bandwidth is used for acquisition while t0lbw bandwidth is used for locked operation. see section 7.7.3 . 1000 = 0.1hz 1001 = 0.3hz 1010 = 0.6hz 1011 = 1.2hz 1100 = 2.5hz 1101 = 4hz 1110 = 8hz 1111 = 18hz (default) 0000 = 35hz 0001 = 70hz 0010 = {unused values, undefined} 0011 = 18hz 0100 = 120hz 0101 = 250hz 0110 = 400hz 0111 = 18hz
________________________________________________________________________________________ ds 3104-se 102 register name: t4cr2 register description: t4 configuration register 2 register address: 6ah bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? pd2g8k[2:0] ? damp[2:0] default 0 0 0 1 0 0 1 1 bits 6 to 4: phase detector 2 gain 8khz (pd2ga8k[2:0]). this field specifies the gain of the t4 phase detector 2 with an input clock of 8khz or less. this value is only used if automatic gain selection is enabled by setting pd2en = 1 in the t4cr3 register. see section 7.7.5 . bits 2 to 0: damping factor (damp[2:0]). this field configures the damping factor of the t4 dpll. damping factor is a function of both damp[2:0] and the t4 dpll bandwidth ( t4bw register). the default value corresponds to a damping factor of 5. see section 7.7.4 . 18hz 35hz 70hz 001 = 1.2 1.2 1.2 010 = 2.5 2.5 2.5 011 = 5 5 5 100 = 5 10 10 101 = 5 10 20 000, 110, and 111 = {unused values} the gain peak for each damping factor is shown below: damping factor gain peak (db) 1.2 0.4 2.5 0.2 5.0 0.1 10 0.06 20 0.03
________________________________________________________________________________________ ds 3104-se 103 register name: t0cr2 register description: t0 configuration register 2 register address: 6bh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? pd2g8k[2:0] ? damp[2:0] default 0 0 0 1 0 0 1 1 bits 6 to 4: phase detector 2 gain, 8khz (pd2g8k[2:0]). this field specifies the gain of the t0 phase detector 2 with an input clock of 8khz or less. this value is only used if automatic gain selection is enabled by setting pd2en = 1 in the t0cr3 register. see section 7.7.5 . bits 2 to 0: damping factor (damp[2:0]). this field configures the damping factor of the t0 dpll. damping factor is a function of both damp [2:0] and the t0 dpll bandwidth ( t0abw and t0lbw ). the default value corresponds to a damping factor of 5. see section 7.7.4 . 4hz 8hz 18hz 35hz 70hz 001 = 5 2.5 1.2 1.2 1.2 010 = 5 5 2.5 2.5 2.5 011 = 5 5 5 5 5 100 = 5 5 5 10 10 101 = 5 5 5 10 20 000, 110, and 111 = {unused values} the gain peak for each damping factor is shown below: damping factor gain peak (db) 1.2 0.4 2.5 0.2 5.0 0.1 10 0.06 20 0.03
________________________________________________________________________________________ ds 3104-se 104 register name: t4cr3 register description: t4 configuration register 3 register address: 6ch bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name pd2en ? pd2g[2:0] default 1 1 0 0 0 0 1 0 bit 7: phase detector 2 gain enable (pd2en). when this bit is set to 1, the t4 phase detector 2 is enabled and the gain is determined by the input locking frequency. if the frequency is greater than 8khz, the gain is set by the pd2g field. if the frequency is less or equal to 8khz, the gain is set by the pd2g8k field in the t4cr2 register. see section 7.7.5 . 0 = disable 1 = enable bits 2 to 0: phase detector 2 gain (pd2g[2:0]). this field specifies the gain of the t4 phase detector 2 when the input frequency is greater than 8khz. this value is only us ed if automatic gain selection is enabled by setting pd2en = 1. see section 7.7.5 . register name: t0cr3 register description: t0 configuration register 3 register address: 6dh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name pd2en ? pd2g[2:0] default 1 1 0 0 0 0 1 0 bit 7: phase detector 2 gain enable (pd2en). when this bit is set to 1, the t0 phase detector 2 is enabled and the gain is determined by the input locking frequency. if the frequency is greater than 8khz, the gain is set by the pd2g field. if the frequency is less or equal to 8khz, the gain is set by the pd2g8k field in the t0cr2 register. see section 7.7.5 . 0 = disable 1 = enable bits 2 to 0: phase detector 2 gain (pd2g[2:0]). this field specifies the gain of the t0 phase detector 2 when the input frequency is greater than 8khz. this value is only us ed if automatic gain selection is enabled by setting pd2en = 1. see section 7.7.5 .
________________________________________________________________________________________ ds 3104-se 105 register name: gpcr register description: gpio configuration register register address: 6eh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name gpio4d gpio3d gpio2d gpio1d gpio4o gpio3o gpio2o gpio1o default 0 0 0 0 0 0 0 0 bit 7: gpio4 direction (gpio4d). this bit configures the data direction for the gpio4 pin. when gpio4 is an input its current state can be read from gpsr :gpio4. when gpio4 is an output, its value is controlled by the gpio4o configuration bit. 0 = input 1 = output bit 6: gpio3 direction (gpio3d). this bit configures the data direction for the gpio3 pin. when gpio3 is an input its current state can be read from gpsr :gpio3. when gpio3 is an output, its value is controlled by the gpio3o configuration bit. 0 = input 1 = output bit 5: gpio2 direction (gpio2d). this bit configures the data direction for the gpio2 pin. when gpio2 is an input its current state can be read from gpsr :gpio2. when gpio2 is an output, its value is controlled by the gpio2o configuration bit. 0 = input 1 = output bit 4: gpio1 direction (gpio1d). this bit configures the data direction for the gpio1 pin. when gpio1 is an input its current state can be read from gpsr :gpio1. when gpi13 is an output, its value is controlled by the gpio1o configuration bit. 0 = input 1 = output bit 3: gpio4 output value (gpio4o). when gpio4 is configured as an out put (gpio4d = 1) then this bit specifies the output value. 0 = low 1 = high bit 2: gpio3 output value (gpio3o). when gpio3 is configured as an out put (gpio3d = 1) then this bit specifies the output value. 0 = low 1 = high bit 1: gpio2 output value (gpio2o). when gpio2 is configured as an out put (gpio2d = 1) then this bit specifies the output value. 0 = low 1 = high bit 0: gpio1 output value (gpio1o). when gpio1 is configured as an out put (gpio1d = 1) then this bit specifies the output value. 0 = low 1 = high
________________________________________________________________________________________ ds 3104-se 106 register name: gpsr register description: gpio status register register address: 6fh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? gpio4 gpio3 gpio2 gpio1 default 0 0 0 0 0 0 0 0 bit 3: gpio4 state (gpio4). this bit indicates the current state of the gpio4 pin. 0 = low 1 = high bit 2: gpio3 state (gpio3). this bit indicates the current state of the gpio3 pin. 0 = low 1 = high bit 2: gpio2 state (gpio2). this bit indicates the current state of the gpio2 pin. 0 = low 1 = high bit 1: gpio1 state (gpio1). this bit indicates the current state of the gpio1 pin. 0 = low 1 = high
________________________________________________________________________________________ ds 3104-se 107 register name: offset1 register description: phase offset register 1 register address: 70h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name offset[7:0] default 0 0 0 0 0 0 0 0 the offset1 and offset2 registers must be read cons ecutively and written cons ecutively. see section 8.3 . bits 7 to 0: phase offset (offset[7:0]). the full 16-bit offset[15:0] field spans this register and the offset2 register. offset is a two?s-complement signed integer th at specifies the desired phase offset between the output clocks and the selected input refer ence. the phase offset in picoseco nds is equal to offset[15:0] x actual_internal_clock_period / 2 11 . if the internal clock is at its nominal frequency of 77.76mhz then the phase offset equation simplifies to offset[15:0] x 6.279ps. if, however, the dpll is lo cked to a reference whose frequency is +1ppm from ideal, for example, then the actu al internal clock period is 1ppm shorter and the phase offset is 1ppm smaller. when the offset field is written, the phase of the out put clocks is automatically ramped to the new offset value to avoid loss of synchronization. to adjust the phase o ffset without changing the phase of the output clocks, use the recalibration process enabled by fscr3 :recal. the offset field is ignored when phase build-out is enabled (pboen = 1 in the mcr10 register) and when the dpll is not locked. see section 7.7.8 . register name: offset2 register description: phase offset register 2 register address: 71h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name offset[15:8] default 0 0 0 0 0 0 0 0 bits 7 to 0: phase offset (offset[15:8]). see the offset1 register description.
________________________________________________________________________________________ ds 3104-se 108 register name: pboff register description: phase build-out offset register register address: 72h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? pboff[5:0] default 0 0 0 0 0 0 0 0 bits 5 to 0: phase build-out offset register (pboff[5:0]). an uncertainty of up to 5ns is introduced each time a phase build-out event occurs. this uncertainty results in a phase hit on the output. over a large number of phase build-out events the mean error should be zero. the pboff field specifies a fixed offset for each phase build-out event to skew the average er ror toward zero. this field is a two?s-complement signed integer. the offset in nanoseconds is pboff[5:0] x 0.101. values greater than 1.4ns or less than -1.4ns can cause internal math errors and should not be used. see section 7.7.7.2 . register name: phlim1 register description: phase limit register 1 register address: 73h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name flen nalol 1 ? ? finelim[2:0] default 1 0 1 0 0 0 1 0 bit 7: fine phase limit enable (flen). this configuration bit enables the fine phase limit specified in the finelim[2:0] field. the fine limit must be disabled for multi-ui jitter tolerance (see phlim2 fields). this field controls both t0 and t4. see section 7.7.6 . 0 = disabled 1 = enabled bit 6: no-activity loss of lock (nalol). the t0 and the t4 dplls can detect t hat an input clock has no activity very quickly (within two clock cycles). when nalol = 0, lo ss-of-lock is not declared when clock cycles are missing, and nearest edge locking ( 180 ) is used when the clock recovers. this gives tolerance to missing cycles. when nalol = 1, loss-of-lock is indicated as soon as no activity is detected, and the device switches to phase/frequency locking ( 360 ). this field controls both t0 and t4. see sections 7.5.3 and 7.7.6 . 0 = no activity does not trigger loss-of-lock 1 = no activity does trigger loss-of-lock bit 5: leave set to 1 (test control). bits 2 to 0: fine phase limit (finelim[2:0]). this field specifies the fine phase limit window, outside of which loss-of-lock is declared. the flen bit enables this feature. the phase of the input clock has to be inside the fine limit window for two seconds before phase lock is declared. loss-of-lock is declared imm ediately if the phase of the input clock is outside the phase limit window. the default va lue of 010 is appropriate for most situations. this field controls both t0 and t4. see section 7.7.6 . 000 = always indicates loss of phase lock?do not use 001 = small phase limit window, 45 to 90 010 = normal phase limit window, 90 to 180 (default) 100, 101, 110, 111 = proportionately larger phase limit window
________________________________________________________________________________________ ds 3104-se 109 register name: phlim2 register description: phase limit register 2 register address: 74h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name clen mcpden usemcpd ? coarselim[3:0] default 1 0 0 0 0 1 0 1 bit 7: coarse phase limit enable (clen). this configuration bit enables the co arse phase limit specified in the coarselim[3:0] field. this field controls both t0 and t4. see section 7.7.6 . 0 = disabled 1 = enabled bit 6: multicycle phase detector enable (mcpden). this configuration bit enables the multicycle phase detector and allows the dpll to tolerate large-amplitude jitter and wande r. the range of this phase detector is the same as the coarse phase limit specified in the coarselim[3:0] field. this field controls both t0 and t4. see section 7.7.5 . 0 = disabled 1 = enabled bit 5: use multicycle phase detector in the dpll algorithm (usemcpd). this configuration bit enables the dpll algorithm to use the multicycle phase detector so t hat a large phase measurement dr ives faster dpll pull-in. when usemcpd = 0, phase measurement is limited to 360 , giving slower pull-in at higher frequencies but with less overshoot. when usemcpd = 1, phase measurement is set as specified in the coarselim[3:0] field, giving faster pull-in. mcpden should be set to 1 when usemcpd = 1. this field controls both t0 and t4. see section 7.7.5 . 0 = disabled 1 = enabled bits 3 to 0: coarse phase limit (coarselim[3:0]). this field specifies the coarse phase limit and the tracking range of the multicycle phase detector. the clen bit enables this feature. if jitter tolerance greater than 0.5ui is required and the input clock is a high frequency signal then the dpll can be configured to track phase errors over many ui using the multicycle phase detector. th is field controls both t0 and t4. see section 7.7.5 and 7.7.6 . 0000 = 1ui 0001 = 3ui 0010 = 7ui 0011 = 15ui 0100 = 31ui 0101 = 63ui 0110 = 127ui 0111 = 255ui 1000 = 511ui 1001 = 1023ui 1010 = 2047ui 1011 = 4095ui 1100 to 1111 = 8191ui
________________________________________________________________________________________ ds 3104-se 110 register name: phmon register description: phase monitor register register address: 76h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name nw ? ? ? ? default 0 0 0 0 0 1 1 0 bit 7: low-frequency input clock noise window (nw). for 2khz, 4khz, or 8khz input clocks, this configuration bit enables a 5% tolerance noise window centered around the ex pected clock edge location. noise-induced edges outside this window are ignored, reducing the possibility of phase hits on the output clocks. this only applies to the t0 dpll and should be enabled only when the t0 dpll is locked to an input and the 180 phase detector is being used. 0 = all edges are recognized by the t0 dpll 1 = only edges within the 5% tolerance window are recognized by the t0 dpll
________________________________________________________________________________________ ds 3104-se 111 register name: phase1 register description: phase register 1 register address: 77h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name phase[7:0] default 0 0 0 0 0 0 0 0 note: the phase1 and phase2 registers must be read consecutively. see section 8.3 . bits 7 to 0: current dpll phase (phase[7:0]). the full 16-bit phase[15:0] field spans this register and the phase2 register. phase is a two?s-complement signed inte ger that indicates the cu rrent value of the phase detector. the value is the output of the phase averager. when t4t0 = 0 in the mcr11 register, phase indicates the current phase of the t0 dpll. when t4t0 = 1, phase indica tes the current phase of the t4 dpll. the averaged phase difference in degrees is equal to phase x 0.707. see section 7.7.10 . register name: phase2 register description: phase register 2 register address: 78h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name phase[15:8] default 0 0 0 0 0 0 0 0 bits 7 to 0: current dpll phase (phase[15:8]). see the phase1 register description. register name: phlkto register description: phase lock timeout register register address: 79h bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name phlktom[1:0] phlkto[5:0] default 0 0 1 1 0 0 1 0 bits 7 to 6: phase lock timeout multiplier (phlktom[1:0]). this field is an unsigned integer that specifies the resolution of the phase lock timeout field phlkto[5:0]. 00 = 2 seconds 01 = 4 seconds 10 = 8 seconds 11 = 16 seconds bits 5 to 0: phase lock timeout (phlkto[5:0]). this field is an unsigned integer that, together with the phlktom[1:0] field, specifies the length of time that the t0 dpll attempts to lock to an input clock before declaring a phase lock alarm (by setting the corresponding lock bit in the isr registers). the timeout period in seconds is phlkto[5:0] x 2^(phlktom[1:0]+1). the state machine remains in the prelocked, prelocked 2, or phase-lost modes for the specified time before declar ing a phase alarm on the selected input. see section 7.7.1 .
________________________________________________________________________________________ ds 3104-se 112 register name: fscr1 register description: frame sync configuration register 1 register address: 7ah bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name 2k8ksrc syncsrc[2:0] 8kinv 8kpul 2kinv 2kpul default 0 0 0 0 0 0 0 0 bit 7: 2khz/8khz source (2k8ksrc). this configuration bit specifies the source for the 2khz and 8khz outputs available on clock outputs. when mcr4 :lkt4t0 = 1 it is always connected to the t0 dpll. see section 7.8.2.3 . 0 = t0 dpll 1 = t4 dpll bit 6 to 4: sync123 source (syncsrc). this field determines whether the sync1, sync2, or sync3 pins are associated with the selected input clock or forced to be associated with a specific input clock. see section 7.9.3 . 0xx = sync[1:3] pins associated with t0 dpll select ed reference ic3 or ic5, ic4 or ic6, ic9, or ic2 1x0 = sync1 pin associated with ic3, sync2 pin associated with ic4 1x1 = sync1 pin associated with ic5, sync2 pin associated with ic6 10x = sync3 pin associated with ic9 11x = sync3 pin associated with ic2 bit 3: 8khz invert (8kinv). when this bit is set to 1 the 8khz si gnal on clock output fsync is inverted. see section 7.8.2.4 . 0 = fsync not inverted 1 = fsync inverted bit 2: 8khz pulse (8kpul). when this bit is set to 1, the 8khz sig nal on clock output fsync is pulsed rather than 50% duty cycle. in this mode output clock oc3 must be enabled, and the pulse width of fsync is equal to the clock period of oc3. see section 7.8.2.4 . 0 = fsync not pulsed; 50% duty cycle 1 = fsync pulsed, with pulse width equal to oc3 period bit 1: 2khz invert (2kinv). when this bit is set to 1 the 2khz signal on clock output mfsync is inverted. see section 7.8.2.4 . 0 = mfsync not inverted 1 = mfsync inverted bit 0: 2khz pulse (2kpul). when this bit is set to 1, the 2khz signal on clock output mfsync is pulsed rather than 50% duty cycle. in this mode output clock oc3 must be enabled, and the pulse width of mfsync is equal to the clock period of oc3. see section 7.8.2.4 . 0 = mfsync not pulsed; 50% duty cycle 1 = mfsync pulsed, with pulse width equal to oc3 period
________________________________________________________________________________________ ds 3104-se 113 register name: fscr2 register description: frame sync configuration register 2 register address: 7bh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name indep ocn phase3[1:0 ] phase2[1:0] phase1[1:0] default 0 0 0 0 0 0 0 0 bit 7: independent frame sync and multiframe sync (indep). when this bit is set to 0, the 8khz frame sync on fsync and the 2khz multiframe sync on mfsync are a ligned with the other output clocks when synchronized with the syncn input. when this bit is 1, the frame sync and multiframe sync are independent of the other output clocks, and their edge position may change without disturbing the other output clocks. see section 7.9.5 . 0 = fsync and mfsync are aligned with other output clocks; all are synchronized by the syncn input 1 = fsync and mfsync are independent of the other clock outputs; only fsync and mfsync are synchronized by the syncn input bit 6: sync oc-n rates (ocn). see section 7.9.2 . 0 = syncn is sampled with a 6.48mhz resolution; the selected reference must be 6.48mhz 1 = if the selected reference is 19.44mhz, syncn is sampled at 19.44mhz and output alignment is to 19.44mhz. if the selected reference is 38.88mhz, syncn is sampled at 38.88mhz. the selected reference must be either 19.44mhz or 38.88mhz bits 5 to 4: external sync sampling phase 3 (phase3[1:0]). this field adjusts the sampling of the sync3 input pin. normally the falling edge of sync3 is aligned with t he falling edge of the selected reference. all ui numbers listed below are ui of the sampling clock. see section 7.9.1 . 00 = coincident 01 = 0.5ui early 10 = 1ui late 11 = 0.5ui late bits 3 to 2: external sync sampling phase 2 (phase2[1:0]). this field adjusts the sampling of the sync2 input pin. normally the falling edge of sync2 is aligned with t he falling edge of the selected reference. all ui numbers listed below are ui of the sampling clock. see section 7.9.1 . 00 = coincident 01 = 0.5ui early 10 = 1ui late 11 = 0.5ui late bits 1 to 0: external sync sampling phase 1 (phase1[1:0]). this field adjusts the sampling of the sync1 input pin. normally the falling edge of sync1 is aligned with t he falling edge of the selected reference. all ui numbers listed below are ui of the sampling clock. see section 7.9.1 . 00 = coincident 01 = 0.5ui early 10 = 1ui late 11 = 0.5ui late
________________________________________________________________________________________ ds 3104-se 114 register name: fscr3 register description: frame sync configuration register 3 register address: 7ch bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name recal monlim[2:0] source[3:0] default 0 0 1 0 1 0 1 1 bit 7: phase offset recalibration (recal). when set to 1 this configuration bit causes a recalibration of the phase offset between the output clocks and the selected refe rence. this process puts the dpll into mini holdover, internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the offset registers, and then switches the dpll out of mini holdover. unlike simply writing the offset registers, the recal process causes no change in the phase offset of the output clocks . recal is automatically reset to 0 when recalibration is complete. see section 7.7.8 . 0 = normal operation 1 = phase offset recalibration bits 6 to 4: sync monitor limit (monlim[2:0]). this field configures the sync monitor limit. when the external frame sync input is misaligned with respect to the mf sync output by the specified number of resampling clock cycles then a frame sync monitor alarm is declared in the fsmon bit of the opstate register. see section 7.9.6 . 000 = 1ui 001 = 2ui 010 = 3ui 011 = 4ui 100 = 5ui 101 = 6ui 110 = 7ui 111 = 8ui bits 3 to 0: sync reference source (source[3:0]). there are two modes of exter nal frame sync operation, a mode using a single input pin (sync1) and a mode using three input pins (sync1, sync2, and sync3). when source = 11xx one of the sync1, sync2, and sync3 pins is selected as the external sync reference depending on which input clock is selected for t0. see section 7.9.7 . when source! = 11xx and automatic external frame sync is enabled (aefsen = 1 in the mcr3 register), the external sync reference on the sync1 pin is enabled when the t0 dpll is locked to the input clock specified by the source field. see section 7.9 . 0000 = {unused value, undefined} 0001 = ic1 0010 = ic2 0011 = ic3 0100 = ic4 0101 = ic5 0110 = ic6 0111 = {unused value, undefined} 1000 = ic8 1001 = ic9 1010 to 1011 = {unused value, undefined} 11xx = sync1, sync2, and sync3 enabled (see section 7.9.7 )
________________________________________________________________________________________ ds 3104-se 115 register name: intcr register description: interrupt configuration register register address: 7dh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ? ? ? ? los gpo od pol default 0 0 0 0 0 0 1 0 bit 3: intreq pin mode (los). when gpo = 0 this bit selects the function of the intreq pin. 0 = the intreq/los pin indicates interrupt requests 1 = the intreq/los pin indicates the real-time stat e of the selected reference activity monitor (see section 7.5.3 ). this function is most useful when external switching mode (section 7.6.5 ) is enabled ( mcr10 :extsw = 1). bit 2: intreq pin general-pu rpose output enable (gpo). when set to 1 this bit configures the interrupt request pin to be a general-purpose output whose value is set by the pol bit. 0 = intreq is function determined by the los bit 1 = intreq is a general-purpose output bit 1: intreq pin open-drain enable (od). when gpo = 0: 0 = intreq is driven in both inactive and active states 1 = intreq is driven high or low in the acti ve state but is high impedance in the inactive state when gpo = 1: 0 = intreq is driven as specified by pol 1 = intreq is high impedance and pol has no effect bit 0: intreq pin polarity (pol). when gpo = 0: 0 = intreq goes low to signal an interrupt request or los = 1 (active low) 1 = intreq goes high to signal interrupt request or los = 1 (active high) when gpo = 1: 0 = intreq driven low 1 = intreq driven high register name: prot register description: protection register register address: 7eh bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name prot[7:0] default 1 0 0 0 0 1 0 1 bits 7 to 0: protection control (prot[7:0]). this field can be used to protect the rest of the register set from inadvertent writes. in protected mode writes to all other registers are ignored. in single unprotected mode, one register (other than prot) can be written, but after that write the device reverts to protected mode (and the value of prot is internally changed to 00h). in fully unprotecte d mode all register can be written without limitation. see section 7.2 . 1000 0101 = fully unprotected mode 1000 0110 = single unprotected mode all other values = protected mode
________________________________________________________________________________________ ds 3104-se 116 9. jtag test access port and boundary scan 9.1 jtag description the DS3104-se supports the sta ndard instruction co des sample/preload, bypass, and extest. optional public instructions included are highz, clamp, and idcode. figure 9-1 shows a block diagram. the DS3104-se contains the following items, which meet the require ments set by the ieee 1149.1 standard test access port and boundary scan architecture: test access port (tap) bypass register tap controller boundary scan register instruction register device identification register the tap has the necessary interface pins, namely jtclk, jtrst , jtdi, jtdo, and jtms. details on these pins can be found in table 6-5. details about the bo undary scan architecture and the tap can be found in ieee 1149.1- 1990, ieee 1149.1a-1993, and ieee 1149.1b-1994. figure 9-1. jtag block diagram boundary scan register device identification register bypass register instruction register test access port controller mux select tri-state jtdi 10k jtms 10k jtclk j trs t 10k ic8
________________________________________________________________________________________ ds 3104-se 117 9.2 jtag tap controller state machine description this section discusses the operation of the tap controlle r state machine. the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk. each of the states denoted in figure 9-2 is described in the following paragraphs. test-logic-reset. upon device power-up, the tap controller starts in the test-logic-reset state. the instruction register contains the idcode in struction. all system logic on the device operates normally. run-test-idle. run-test-idle is used between scan operations or dur ing specific tests. the instruction register and all test registers remain idle. select-dr-scan. all test registers retain their pr evious state. with jtms low, a rising edge of jtclk moves the controller into the capture-dr state and initiates a scan sequence. jtms high moves the controller to the select- ir-scan state. capture-dr. data can be parallel-loaded into the test register se lected by the current instru ction. if the instruction does not call for a parallel load or the selected test register does not allow parallel loads, the register remains at its current value. on the rising edge of jtclk, the controller goe s to the shift-dr state if jtms is low or to the exit1- dr state if jtms is high. shift-dr. the test register selected by the current instru ction is connected between jtdi and jtdo and data is shifted one stage toward the serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the serial path, it maintains it s previous state. exit1-dr. while in this state, a rising edge on jtclk with jtms high puts the controller in the update-dr state, which terminates the scanning process. a rising edge on jtclk with jtms low puts the controller in the pause-dr state. pause-dr. shifting of the test registers is halted while in this state. all test register s selected by the current instruction retain their previous state. the controller re mains in this state while jtms is low. a rising edge on jtclk with jtms high puts the cont roller in the exit2-dr state. exit2-dr. while in this state, a rising edge on jtclk with jtms high puts the controller in the update-dr state and terminates the scanning process. a rising edge on jtclk with jtms low puts the controller in the shift-dr state. update-dr. a falling edge on jtclk while in the update-dr state latches the data from the shift register path of the test registers into the data output latches. this pr events changes at the parallel output because of changes in the shift register. a rising edge on jtclk with jtms low put s the controller in the run-test-idle state. with jtms high, the controller enters t he select-dr-scan state. select-ir-scan. all test registers retain their pr evious state. the instruction regi ster remains unchanged during this state. with jtms low, a rising edge on jtclk moves the c ontroller into the capture-ir state and initiates a scan sequence for the instruction register. jtms high duri ng a rising edge on jtclk puts the controller back into the test-logic-reset state. capture-ir. the capture-ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jt clk, the controller enters the exit1-ir state. if jtms is low on the rising edge of jtclk, the controller enters the shift-ir state. shift-ir. in this state, the instruction register?s shift regist er is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk toward the serial output. the parallel register and the test registers remain at their previous states. a rising edge on jtclk wi th jtms high moves the controller to the exit1-ir state. a rising edge on jtclk with jtms low keeps the controlle r in the shift-ir state, while moving data one stage through the instruction shift register.
________________________________________________________________________________________ ds 3104-se 118 exit1-ir. a rising edge on jtclk with jtms low puts the controll er in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller enters the u pdate-ir state and terminates the scanning process. pause-ir. shifting of the instruction register is halted tempor arily. with jtms high, a rising edge on jtclk puts the controller in the exit2-ir state. t he controller remains in the pause-ir st ate if jtms is low during a rising edge on jtclk. exit2-ir. a rising edge on jtclk with jtms high puts the cont roller in the update-ir st ate. the controller loops back to the shift-ir state if jtms is low during a rising edge of jtclk in this state. update-ir. the instruction shifted into the instruction shift regi ster is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instructio n becomes the current instruction. a rising edge on jtclk with jtms low puts the controller in the run-test-idle state. wi th jtms high, the controller enters the select-dr-scan state. figure 9-2. jtag tap controller state machine test-logic-reset run-test/idle select dr-scan 1 0 capture-dr 1 0 shift-dr 0 1 exit1- dr 1 0 pause-dr 1 exit2-dr 1 update-dr 0 0 1 select ir-scan 1 0 capture-ir 0 shift-ir 0 1 exit1-ir 1 0 pause-ir 1 exit2-ir 1 update-ir 0 0 1 0 0 1 0 1 0 1
________________________________________________________________________________________ ds 3104-se 119 9.3 jtag instruction register and instructions the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift-ir state, the instruction sh ift register is connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low shifts data one stage toward t he serial output at jtdo. a rising edge on jtclk in the exit1-ir state or the exit2-ir state with jtms high move s the controller to the update- ir state. the falling edge of that same jtclk latches the dat a in the instruction shift register to the instruction parallel output. table 9-1 shows the instructions s upported by the DS3104-se and thei r respective operational binary codes. table 9-1. jtag instruction codes instructions selected register instruction codes sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcode device identification 001 sample/preload. sample/reload is a mandatory instruction for the ieee 1149.1 sp ecification. this instruction supports two functions. first, the digital i/o s of the device can be sampled at the boundary scan register, using the capture-dr state, without interfering with the device?s normal operation. second, data can be shifted into the boundary scan register th rough jtdi using the shift-dr state. extest. extest allows testing of the interconnections to t he device. when the extest instruction is latched in the instruction register, the following actions occur: (1) once the extest instruction is enabled through the update-ir state, the parallel outputs of the digital output pins are driven. (2) the boundary scan register is connected between jtdi and jtdo. (3) the capture-dr state samples all digital inputs into the boundary scan register. bypass. when the bypass instruction is latched into the parallel instruction register, jtdi is connected to jtdo through the 1-bit bypass register. this allows data to pass from jtdi to jtdo without affecting the device?s normal operation. idcode. when the idcode instruction is latched into the para llel instruction register, the device identification register is selected. the device id code is loaded into t he device identification register on the rising edge of jtclk, following entry into the capture-dr state. shift-dr can be used to shift the id code out serially through jtdo. during test-logic-reset, the id code is forced in to the instruction register?s parallel output. highz. all digital outputs are placed into a high-impedance st ate. the bypass register is connected between jtdi and jtdo. clamp. all digital output pins output data from the bounda ry scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs do not change during the clamp instruction.
________________________________________________________________________________________ ds 3104-se 120 9.4 jtag test registers ieee 1149.1 requires a minimum of two test registers?t he bypass register and the boundary scan register. an optional test register, the identificati on register, has been included in the device design. it is used with the idcode instruction and the test-logic-res et state of the tap controller. bypass register. this is a single 1-bit shift register used wi th the bypass, clamp, and hi ghz instructions to provide a short path between jtdi and jtdo. boundary scan register. this register contains a shift register path and a latched parallel output for control cells and digital i/o cells. bsdl files are available at www.maxim-ic.com/techsupport/telecom/bsdl.htm . identification register. this register contains a 32-bit shift regist er and a 32-bit latched parallel output. it is selected during the idcode instruction and when the tap c ontroller is in the test-logic-reset state. the device identification code for the DS3104-se is shown in table 9-2. table 9-2. jtag id code device revision device code manufacturer code required DS3104-se consult factory 0000000010100010 00010100001 1
________________________________________________________________________________________ ds 3104-se 121 10. electrical characteristics absolute maximum ratings voltage range on any pin with respect to v ss (except v dd )??.???????????????..-0.3v to +5.5v supply voltage range (v dd ) with respect to v ss ??.????.???????????????..-0.3v to +1.98v supply voltage range (v ddio ) with respect to v ss ?????.????????????????.-0.3v to +3.63v ambient operating temperature range ??????????????????????????.-40c to +85c junction operating temperature range?????????????????????????..-40c to +125c storage temperature range??????????????????????????????..-55c to +125c soldering temperature??????????????????????s ee ipc/jedec j-std-020 specification stresses beyond those listed under ?absolute maximum ratings? may c ause permanent damage to the device. these are stress rating s only, and functional operation of the device at t hese or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. exposure to the absolute ma ximum rating conditions for ex tended periods may affect device. ambient operating tempe rature range when device is mounted on a four-layer jedec test board with no airflow. note: the typical values listed in the tables of section 10 are not production tested. 10.1 dc characteristics table 10-1. recommended dc operating conditions parameter symbol conditions min typ max units supply voltage, core vdd 1.62 1.8 1.98 v supply voltage, i/o vddio 3.135 3.3 3.465 v ambient temperature range t a -40 +85 c junction temperature range t j -40 +125 c table 10-2. dc characteristics (vdd = 1.8v 10%; vddio = 3.3v 5%, t a = -40c to +85c) parameter symbol conditions min typ max units supply current, core i dd (notes 1, 2) 160 185 ma supply current, i/o i ddio (notes 1, 2) 29 45 ma supply current from vdd_oc45 when outputs oc4 and oc5 enabled i ddoc45 (note 3) 16 ma supply current from vdd_oc67 when outputs oc6 and oc7 enabled i ddoc67 (note 3) 16 ma input capacitance c in 5 pf output capacitance c out 7 pf note 1: 12.800mhz clock applied to refclk and 19.44 mhz clock applied to one cmos/ttl input clock pin. one 19.44mhz cmos/ttl output clock pin driving 100pf load; all other inputs at vddio or grounded; all other outputs disabled and open. note 2: typ current measured at vdd = 1.8v and vddio = 3.3v, max current measured at vdd = 1.98v and vddio = 3.465v. note 3: 19.44mhz output clock frequency, driving the load shown in figure 10-1 .
________________________________________________________________________________________ ds 3104-se 122 table 10-3. cmos/ttl pins (vdd = 1.8v 10%; vddio = 3.3v 5%, t a = -40c to +85c) parameter symbol conditions min typ max units input high voltage v ih 2.0 5.5 v input low voltage v il -0.3 +0.8 v input leakage i il (note 1) -10 +10 a input leakage, pins with internal pullup resistor (50k typ) i ilpu (note 1) -85 +10 a input leakage, pins with internal pulldown resistor (50k typ) i ilpd (note 1) -10 +85 a output leakage (when high impedance) i lo (note 1) -10 +10 a output high voltage (i o = -4.0ma) v oh 2.4 vddio v output high voltage (i o = -4.0ma) v oh (note 2) 2.0 vddiob v output low voltage (i o = +4.0ma) v ol 0 0.4 v note 1: 0v < v in < vddio for all other digital inputs. note 2: for oc1b through oc5b when vddiob = 2.5v. table 10-4. lvds/lvpecl input pins (vdd = 1.8v 10%; vddio = 3.3v 5%, t a = -40c to +85c) parameter symbol conditions min typ max units input voltage tolerance v tol (note 1) 0 vddio v input voltage range v in v id = 100mv 0 2.4 v input differential voltage v id 0.1 1.4 v input differential logic threshold v idth -100 +100 mv note 1: the device can tolerate this range of voltages w.r.t. vss on its icxpos and icxneg pins without being damaged. proper operation of the differential input circuitry is only guarant eed when the other specifications in this table are met. table 10-5. lvds output pins (vdd = 1.8v 10%; vddio = 3.3v 5%, t a = -40c to +85c) parameter symbol conditions min typ max units output high voltage v ohlvds (note 1) 1.6 v output low voltage v ollvds (note 1) 0.9 v differential output voltage v odlvds 247 350 454 mv output offset (common mode) voltage v oslvds 25 c (note 1) 1.125 1.25 1.375 v difference in magnitude of output differential voltage for complementary states v doslvds 25 mv note 1: with 100 load across the differential outputs. note 2: the differential outputs can easily be interfaced to lvds, l vpecl, and cml inputs on neighboring ics using a few external passive components. see maxim app note hfan-1.0 for details.
________________________________________________________________________________________ ds 3104-se 123 table 10-6. lvpecl level-c ompatible output pins (vdd = 1.8v 10%; vddio = 3.3v 5%, t a = -40c to +85c) parameter symbol conditions min typ max units differential output voltage v odpecl 595 700 930 mv output offset (common mode) voltage v ospecl 25 c (note 1) 0.8 v difference in magnitude of output differential voltage for complementary states v dospecl 50 mv note 1: with 100 load across the differential outputs. note 2: the differential outputs can easily be interfaced to lvds, l vpecl, and cml inputs on neighboring ics using a few external passive components. see maxim app note hfan-1.0 for details. figure 10-1. recommended term ination for lvds pins DS3104 lvds io icnpos iicnneg 100 lvds driver lvds rcvr figure 10-2. recommended term ination for lvpecl signals on lvds input pins DS3104 lvds inputs icnpos icnneg 130 130 82 82 50 50 gnd 3.3v lvpecl driver
________________________________________________________________________________________ ds 3104-se 124 figure 10-3. recommended term ination for lvpecl-compatible output pins DS3104 lvpecl level- outputs ocnpos ocnneg 5 0 5 0 82 .01 uf 1 30 130 gnd 3.3v pecl rcvr 8 2 compatible
________________________________________________________________________________________ ds 3104-se 125 10.2 input clock timing table 10-7. input clock timing (vdd = 1.8v 10%; vddio = 3.3v 5%, t a = -40c to +85c) parameter symbol min typ max input clock period, cmos/ttl input pins t cyc 8ns (125mhz) 500 s (2khz) input clock period, lv ds/lvpecl input pins t cyc 6.4ns (156.25mhz) 500 s (2khz) input clock high, low time t h , t l 3ns or 30% of t cyc , whichever is smaller 10.3 output clock timing table 10-8. input clock to output clock delay input frequency output frequency delay, input clock edge to output clock edge (ns) 8khz 8khz 0.0 1.5 6.48mhz 6.48mhz 0.0 1.5 19.44mhz 19.44mhz 0.0 1.5 25.92mhz 25.92mhz 0.0 1.5 38.88mhz 38.88mhz 0.0 1.5 51.84mhz 51.84mhz 0.0 1.5 77.76mhz 77.76mhz 0.0 1.5 155.52mhz 155.52mhz 0.0 1.5 table 10-9. output clock phase ali gnment, frame sync alignment mode output frequency delay, mfsync falling edge to output clock falling edge (ns) 8khz (fsync) 0.0 0.5 2khz 0.0 0.5 8khz 0.0 0.5 1.544mhz 0.0 1.25 2.048mhz 0.0 1.25 44.736mhz -2.0 1.25 34.368mhz -2.0 1.25 6.48mhz -2.0 1.25 19.44mhz -2.0 1.25 25.92mhz -2.0 1.25 38.88mhz -2.0 1.25 51.84mhz -2.0 1.25 77.76mhz -2.0 1.25 155.52mhz -2.0 1.25 311.04mhz -2.0 1.25ns see section 7.9 for details on frame sync alignment and the sync[1:3] pins.
________________________________________________________________________________________ ds 3104-se 126 10.4 spi interface timing table 10-10. spi interface timing (vdd = 1.8v 10%; vddio = 3.3v 5%, t a = -40c to +85c) (see figure 10-4 .) parameter ( note 1 ) symbol min typ max units sclk frequency f bus 6 mhz sclk cycle time t cyc 100 ns cs setup to first sclk edge t suc 15 ns cs hold time after last sclk edge t hdc 15 ns sclk high time t clkh 50 ns sclk low time t clkl 50 ns sdi data setup time t sui 5 ns sdi data hold time t hdi 15 ns sdo enable time (high-impedance to output active) t en 0 ns sdo disable time (output active to high-impedance) t dis 25 ns sdo data valid time t dv 50 ns sdo data hold time after update sclk edge t hdo 5 ns note 1: all timing is specified with 100pf load on all spi pins.
________________________________________________________________________________________ ds 3104-se 127 figure 10-4. spi interface timing diagram cs sclk, cpol=0 sclk, cpol=1 t sui t hdi sdi t cyc t suc t clkh t clkl t clkl t clkh t hdc sdo t en t dv t hdo t dis cpha = 0 cpha = 1 cs sclk, cpol=0 sclk, cpol=1 t cyc t suc t clkh t clkl t clkl t hdc t sui t hdi sdi sdo t en t dv t hdo t dis t clkh
________________________________________________________________________________________ ds 3104-se 128 10.5 jtag interface timing table 10-11. jtag interface timing (vdd = 1.8v 10%; vddio = 3.3v 5%, t a = -40c to +85c.) (see figure 10-5 .) parameter symbol min typ max units jtclk clock period t1 1000 ns jtclk clock high/low time (note 1) t2/t3 50 500 ns jtclk to jtdi, jtms setup time t4 50 ns jtclk to jtdi, jtms hold time t5 50 ns jtclk to jtdo delay t6 2 50 ns jtclk to jtdo high-impedance delay (note 2) t7 2 50 ns jtrst width low time t8 100 ns note 1: clock can be stopped high or low. note 2: not tested during production test. figure 10-5. jtag timing diagram t1 jtdo t4 t5 t2 t3 t7 jtdi, jtms, j trs t t6 jtrst t8 jtcl k
________________________________________________________________________________________ ds 3104-se 129 10.6 reset pin timing table 10-12. reset pin timing (vdd = 1.8v 10%; vddio = 3.3v 5%, t a = -40c to +85c) (see figure 10-6 .) parameter symbol min typ max units rst low time (note 1) t1 1000 ns sonsdh, srcsw setup time to rst t2 0 ns sonsdh, srcsw hold time from rst t3 50 ns note 1: rst should be held low while the refclk osc illator stabilizes. it is recommended to force rst low during power-up. the 1000ns minimum time applies if the rst pulse is applied any time after the device has powered up and the oscillator has stabilized. figure 10-6. reset pin timing diagram r st sonsdh srcsw valid x x t2 t3 t1
________________________________________________________________________________________ ds 3104-se 130 11. pin assignments table 11-1 below lists pin assignments sorted in alphabetical order by pin name. figure 11-1 shows pin assignments arranged by pin number. table 11-1. pin assignments sorted by signal name pin name pin number pin name pin number avdd_pll1 b2 oc3 b7 avdd_pll2 c2 oc3b/gpio3 b5 avdd_pll3 f2 oc4 a3 avdd_pll4 f3 oc4b a6 avss_pll1 a1 oc4neg d1 avss_pll2 c3 oc4pos d2 avss_pll3 f1 oc5 a4 avss_pll4 g2 oc5b b6 cpha e7 oc5neg e1 cpol d7 oc5pos e2 cs d9 oc6neg j2 fsync h1 oc6pos h2 ic1neg j5 oc7neg j3 ic1pos h5 oc7pos h3 ic2neg j7 refclk c1 ic2pos h7 rst b9 ic3 j8 sclk c9 ic4 j9 sdi e8 ic5neg j4 sdo c7 ic5pos h4 sonsdh/gpio4 b3 ic6neg j6 srcsw g1 ic6pos h6 srfail f7 ic8 f9 sync1 h8 ic9 g9 sync2 h9 intreq/los b1 sync3 g8 jtclk a9 test a2 jtdi a8 vdd c5, e6, g6 jtdo c8 vdd_oc45 e3 jtms e9 vdd_oc67 g5 jtrst f8 vddio c4, d6, f6, g3 lock g7 vddiob c6 mfsync j1 vss d4, d5, e4, e5, f4, f5 oc1 b8 vss_oc45 d3 oc1b/gpio1 b4 vss_oc67 g4 oc2 a7 wdt d8 oc2b/gpio2 a5
________________________________________________________________________________________ ds 3104-se 131 figure 11-1. pin assignment diagram 1 2 3 4 5 6 7 8 9 a avss_pll1 test oc4 oc5 oc2b/ gpio2 oc4b oc2 jtdi jtclk b intreq/ los avdd_pll1 sonsdh/ gpio4 oc1b/ gpio1 oc3b/ gpio3 oc5b oc3 oc1 rst c refclk avdd_pll2 avss_pll2 vddio vdd vddiob sdo jtdo sclk d oc4neg oc4pos vss_oc45 vss vss vddio cpol wdt cs e oc5neg oc5pos vdd_oc45 vss vss vdd cpha sdi jtms f avss_pll3 avdd_pll3 avdd_pll4 vss vss vddio srfail jtrst ic8 g srcsw avss_pll4 vddio vss_oc67 vdd_oc67 vdd lock sync3 ic9 h fsync oc6pos oc7pos ic5pos ic1pos ic6pos ic2pos sync1 sync2 j mfsync oc6neg oc7neg ic5neg ic1neg ic6neg ic2neg ic3 ic4 high-speed analog low-speed analog high-speed digital low-speed digital v ddio 3.3v v ddiob 3.3v or 2.5v v dd 1.8v analog v dd 1.8v v ss analog v ss n.c. = no connection. lead is not co nnected to anything inside the device.
________________________________________________________________________________________ ds 3104-se 132 12. package information the latest package outline drawing for the 10mm x 10mm, 81-lead csbga package is 56-g6009-001 and can be found on the maxim website at www.maxim-ic.com/dallaspackinfo . table 12-1. csbga package thermal properties, natural convection parameter min typ max ambient temperature (note 1) -40 c +85 c junction temperature -40 c +125 c theta - ja ( ja ) (note 2) 33.8 c/w theta - jb ( jb ) 18.2 c/w theta - jc ( jc ) 9.0 c/w psi-jb 17.8 c/w psi-jt 0.22 c/w note 1: the package is mounted on a four - layer jedec standard test board with no airflow and dissipating maximum power. note 2: theta - ja ( ja ) is the junction to ambient thermal resistance, when the package is mounted on a four - layer jedec standard test board with no airflow and dissipating maximum power.
________________________________________________________________________________________ ds 3104-se 133 13. acronyms and abbreviations ais alarm indication signal ami alternate mark inversion apll analog phase locked loop bits building integrated timing supply bpv bipolar violation dfs digital frequency synthesis dpll digital phase locked loop esf extended superframe exz excessive zeros gbe gigabit ethernet i/o input/output los loss of signal lvds low-voltage differential signal lvpecl low-voltage positive emitter-coupled logic mtie maximum time interval error ocxo oven controlled crystal oscillator oof out of frame alignment pbo phase build-out pfd phase/frequency detector pll phase locked loop ppb parts per billion ppm parts per million pk-pk peak-to-peak rms root-mean-square rai remote alarm indication ro read-only r/w read/write sdh synchronous digital hierarchy sec sdh equipment clock sets synchronous equipment timing source sf superframe sonet synchronous optical network ssm synchronization status message ssu synchronization supply unit stm synchronous transport module tdev time deviation tcxo temperature-compen sated crystal oscillator ui unit interval ui p-p unit interval, peak to peak xo crystal oscillator
________________________________________________________________________________________ ds 3104-se 134 14. trademark acknowledgements spi is a trademark of motorola, inc. motorola is a registered trademark of motorola, inc. telcordia is a registered trademark of telcordia technologies, inc.
________________________________________________________________________________________ ds 3104-se maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the ci rcuitry and specifications wi thout notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 135 ? 2007 maxim integrated products is a registered trademark of maxim integrated products. 15. data sheet revision history revision date description 060507 initial data sheet release. 070507 (page 1) corrected typo in features bullet, pr ogrammable pll bandwidth, from 1hz to 0.1hz (0.1hz to 400hz). 071807 (page 6) added reference to g.8262 to table 1-1 . (page 14). in the oc3b pin description in table 6-2 , corrected typo by changing oc2ben to oc3ben. (page 15) in table 6-3 , changed pin name intreq/srfail to intreq/los and changed the pin description to clarify its non-intreq function. (page 16) in table 6-6 , corrected avdd_pll4 and avss_pll4 des criptions to say they are the power supply for t0 apll2 rather than t0 apll. (page 52) in section 7.11 , emphasized the need for rst pin assertion and added requirement to least 100s after reset is deasserted before initializing the device. (page 58) in the msr2 :srfail bit description, deleted references to the intreq/srfail pin and to intcr :srfail. (page 75) in the mcr4 register description header, corrected typo by renaming bit 6 from ?t4digfb? to ???. (page 107) deleted reference to nonexistent pmpben bit in the offset1 register. (page 115) changed intcr :srfail to los and changed its bit description to clarify function. updated references to this bit in other intcr bit descriptions. (page 130) in table 11-1 , changed intreq to intreq/los. (page 131) in figure 11-1 , changed intreq to intreq/los.

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